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參數(shù)資料
| 型號： | DS3994 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | 4-Channel Cold-Cathode Fluorescent Lamp Controller |
| 中文描述： | 4通道冷陰極熒光燈控制器 |
| 文件頁數(shù)： | 23/28頁 |
| 文件大?。?/td> | 557K |
| 代理商： | DS3994 |
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I
2
C Definitions
The following terminology is commonly used to
describe I
2
C data transfers.
Master Device:
The master device controls the slave
devices on the bus. The master device generates SCL
clock pulses, start, and stop conditions.
Slave Devices:
Slave devices send and receive data
at the master
’
s request.
Bus Idle or Not Busy:
Time between stop and start
conditions when both SDA and SCL are inactive and in
their logic-high states.
Start Condition:
A start condition is generated by the
master to initiate a new data transfer with a slave.
Transitioning SDA from high to low while SCL remains
high generates a start condition. See the timing dia-
gram for applicable timing.
Stop Condition:
A stop condition is generated by the
master to end a data transfer with a slave. Transitioning
SDA from low to high while SCL remains high gener-
ates a stop condition. See the timing diagram for
applicable timing.
Repeated Start Condition:
The master can use a
repeated start condition at the end of one data transfer
to indicate that it will immediately initiate a new data
transfer following the current one. Repeated starts are
commonly used during read operations to identify a
specific memory address to begin a data transfer. A
repeated start condition is issued identically to a nor-
mal start condition. See the timing diagram for applica-
ble timing.
Bit Write:
Transitions of SDA must occur during the low
state of SCL. The data on SDA must remain valid and
unchanged during the entire high pulse of SCL plus the
setup and hold time requirements (see Figure 10). Data is
shifted into the device during the rising edge of the SCL.
Bit Read:
At the end of a write operation, the master
must release the SDA bus line for the proper amount of
setup time (see Figure 10) before the next rising edge
of SCL during a bit read. The device shifts out each bit
of data on SDA at the falling edge of the previous SCL
pulse and the data bit is valid at the rising edge of the
current SCL pulse. Remember that the master gener-
ates all SCL clock pulses including when it is reading
bits from the slave.
Acknowledgement (ACK and NACK):
An acknowl-
edgement (ACK) or not acknowledge (NACK) is always
the 9th bit transmitted during a byte transfer. The
device receiving data (the master during a read or the
slave during a write operation) performs an ACK by
transmitting a zero during the 9th bit. A device per-
forms a NACK by transmitting a one during the 9th bit.
Timing (Figure 10) for the ACK and NACK is identical to
all other bit writes. An ACK is the acknowledgment that
the device is properly receiving data. A NACK is used
to terminate a read sequence or as an indication that
the device is not receiving data.
D
4-Channel Cold-Cathode
Fluorescent Lamp Controller
____________________________________________________________________
23
Figure 10. I
2
C Timing Diagram
SDA
SCL
t
HD:STA
t
LOW
t
HIGH
t
R
t
F
t
BUF
t
HD:DAT
t
SU:DAT
REPEATED
START
t
SU:STA
t
HD:STA
t
SU:STO
t
SP
STOP
NOTE: TIMING IS REFERENCED TO V
IL(MAX)
AND V
IH(MIN)
.
START
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DS3994Z+ | 功能描述:顯示驅(qū)動器和控制器 4-Ch CCFL Controller RoHS:否 制造商:Panasonic Electronic Components 工作電源電壓:2.7 V to 5.5 V 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Reel |
| DS3994Z+T&R | 制造商:Maxim Integrated Products 功能描述:2ND GEN 4CH CCFL CON SOIC-28 T&R LF - Tape and Reel 制造商:Maxim Integrated Products 功能描述:IC CCFL CNTRLR 4CH 28-SOIC |
| DS3994Z+T&R | 功能描述:顯示驅(qū)動器和控制器 4-Ch CCFL Controller RoHS:否 制造商:Panasonic Electronic Components 工作電源電壓:2.7 V to 5.5 V 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Reel |
| DS3994Z+W | 功能描述:顯示驅(qū)動器和控制器 4-Ch CCFL Controller RoHS:否 制造商:Panasonic Electronic Components 工作電源電壓:2.7 V to 5.5 V 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Reel |
| DS3CC | 制造商:Thomas & Betts 功能描述:30A,MG,CUP CAP |
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