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參數(shù)資料
| 型號： | DS3832C-311 |
| 英文描述： | 3.3V, 32Mb Advanced NV SRAM with Clock |
| 中文描述： | 3.3，32MB的高級非易失SRAM，帶有時鐘 |
| 文件頁數(shù)： | 7/18頁 |
| 文件大?。?/td> | 428K |
| 代理商： | DS3832C-311 |
DS3832C-311
7 of 18
TIME-OF-DAY ALARM MASK BITS
(Figure 4)
REGISTER
MINUTES
HOURS
1
1
DAYS
1
ALARM
ALARM ONCE PER MINUTE
0
1
1
ALARM WHEN MINUTES MATCH
0
0
1
ALARM WHEN MINUTES AND HOURS MATCH
0
0
0
ALARM WHEN MINUTES, HOURS, AND DAYS MATCH
NOTE:
Any other bit combinations produce illogical operation.
CLOCK REGISTERS
The DS3832C-311 clock has 14 8-bit internal registers that contain all timekeeping, alarm, watchdog, and
control information. The clock, calendar, alarm, and watchdog registers are memory locations that contain
both external (user-accessible) and internal copies of the data. The external copies are independent of
internal functions except that they are updated periodically by simultaneous transfer from the incremented
internal copies. The command register bits are affected by both internal and external functions. In addition
to the 14 registers, the clock also contains 50 bytes of user RAM. Clock registers 0, 1, 2, 4, 6, 8, 9, and A
(hex) contain day, date, and time information stored in binary-code decimal (BCD) format. Registers 3, 5,
and 7 contain time-of-day alarm information also stored in BCD format. Register B is the command
register containing eight 1-bit binary fields. Registers C and D contain watchdog alarm information stored
in BCD format. Addresses E through 3F are general-purpose user RAM.
DAY, DATE AND TIME REGISTERS
Registers 0, 1, 2, 4, 6, 8, 9, and A (hex) contain day, date, and time information in BCD format. Eleven
bits within these eight registers are not used and will always read zero regardless of how they are written.
Bits 6 and 7 in the month register (register 9) are binary control bits.
When set to logic 0,
EOSC
(register 9, bit 7) enables the clock oscillator. This bit is normally turned on by
the user during device initialization. The oscillator can be turned on and off as needed by enabling or
disabling this bit.
Register 8 bit 7, INP, controls the logic state of the
INTP
output pin of the clock device. Because this
logic feature is not supported in the DS3832C-311, INP should be set to a logic zero.
Register 9 bit 6,
ESQW
, enables and disables the output of a 1024Hz square wave. Because this feature is
not supported in the DS3832C-311,
ESQW
should be set to logic one.
Bit 6 of the hour register (register 4) is defined as the 12- or 24-hour select bit. When set to logic one, the
12-hour format is selected. In the 12-hour format, bit 5 is the AM/PM bit with logic 1 being PM. In the
24-hour mode, bit 5 is the upper-order 10-hour bit (set for hours 20 to 23).
The external day, date, and time registers are updated from their internal counterparts every 0.01 seconds
except when the TE bit (bit 7 of register B) is set low or the clock oscillator is not running (
EOSC
high).
Setting TE low freezes the external day, date, and time registers at their present values allowing all the
registers to be read or written without any of them being updated from the internal registers. After the
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