
DS3803
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READ MODE
The DS3803 executes a read cycle whenever WE
(Write enable) is inactive (high) and CE (Chip Enable)
and OE (Output Enable) are active (low). The unique
address specified by the 15 address inputs (A
0
– A
14
)
defines which byte of data is to be accessed from the
selected SRAMs. Valid data will be available to the data
output drivers within t
ACC
(Access Time) after the last
address input signal is stable, providing that CE and OE
(Output Enable) access times are also satisfied. If CE
and OE access times are not satisfied, then data access
must be measured from the later occurring signal and
the limiting parameter is either t
CO
for CE or t
OE
for OE
rather than t
ACC
.
WRITE MODE
The DS3803 executes a write cycle whenever both WE
and CE signals are in the active (low) state after address
inputs are stable. The later occurring falling edge of CE
or WE will determine the start of the write cycle. The
write cycle is terminated by the earlier rising edge of CE
or WE. All address inputs must be kept valid throughout
the write cycle. WE must return to the high state for a
minimum recovery time (t
WR
) before another cycle can
be initiated. The OE control signal should be kept inac-
tive (high) during write cycles to avoid bus contention.
However, if the output drivers are enabled (CE and OE
active) then WE will disable the outputs in t
ODW
from its
falling edge.
DATA RETENTION MODE
The DS3803 provides full functional capability for V
CC
greater than 4.5 volts and write protects by 4.25 volts.
Data is maintained in the absence of V
CC
without any
additional support circuitry. The nonvolatile static RAM
constantly monitors V
CC
. Should the supply voltage
decay, the NV SRAM automatically write protects itself,
all inputs become dont care, and all outputs become
high impedance. As V
CC
falls below approximately
3.0 volts, power switching circuits connect the lithium
energy sources to the RAMs to retain data. During pow-
er–up, when V
CC
rises above approximately 3.0 volts,
the power switching circuits connect external V
CC
to the
RAMs and disconnects the lithium energy source. Nor-
mal RAM operation can resume after V
CC
exceeds 4.5
volts.
The DS3803 checks battery status to warn of potential
data loss. Each time that V
CC
power is restored to the
DS3803, the battery voltages are checked with preci-
sion comparators. If both batteries providing backup
power to a particular SRAM are less than 2.0 volts, the
second memory access to that SRAM is inhibited. Bat-
tery status for each SRAM can, therefore, be deter-
mined by a three–step process. First, a read cycle is
performed to any location within that SRAM, in order to
save the contents of that location. A subsequent write
cycle can then be executed to the same memory loca-
tion, altering data. If a subsequent read cycle fails to
verify the written data, then battery voltage for that
SRAM is less than 2.0V and data is in danger of being
lost.
The DS3803 also provides battery redundancy. In
many applications data integrity is paramount. The
DS3803 provides two batteries for each SRAM and an
internal isolation switch to select between them. During
battery backup, the battery with the highest voltage is
selected for use. If one battery fails, the other automati-
cally takes over. The switch between batteries is trans-
parent to the user.