I2C Gamma and VCOM Buffer with EEP" />
參數(shù)資料
型號: DS3514T+T&R
廠商: Maxim Integrated Products
文件頁數(shù): 8/21頁
文件大?。?/td> 0K
描述: IC I2C GAMMA/VCOM BUFF 48-TQFN
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,500
應用: TFT-LCD 面板:伽瑪緩沖器,VCOM 驅(qū)動器
輸出類型: 滿擺幅
電路數(shù): 14
電流 - 電源: 5mA
電流 - 輸出 / 通道: 4mA
電壓 - 電源,單路/雙路(±): 9 V ~ 15 V
安裝類型: 表面貼裝
封裝/外殼: 48-WFQFN 裸露焊盤
供應商設備封裝: 48-TQFN-EP(7x7)
包裝: 帶卷 (TR)
DS3514
I2C Gamma and VCOM Buffer with EEPROM
16
______________________________________________________________________________________
Control Register 48h: Control Register (CR)
FACTORY DEFAULT
20h
MEMORY TYPE
NV
48h
x
BIAS1
BIAS0
x
MODE1
MODE0
BIT 7
BIT 0
Bits 7:6
Reserved
Bits 5:4
VCOM and Gamma Bias Current Control Bits (BIAS[1:0]):
00 = 60%
01 = 80%
10 = 100% (default)
11 = 150%
Bits 3:2
Reserved
Bits 1:0
DS3514 Mode (MODE[1:0]):
00 = S0/S1 pins are used to select the desired bank (A–D) (default).
01 = SOFT S0/S1 (bits) are used to select the desired bank (A–D).
1X = Latch A is used to control the DACs.
Status Bits Register 4Ah: Real-Time Indicator of Logic State on LD, S1, and S0 Pins
FACTORY DEFAULT
MEMORY TYPE
Read Only
4Ah
LD
x
S1
S0
BIT 7
BIT 0
This is an example of how the bits are arranged for a typical GDATx memory location. GDATx has 10 bits that are
arranged in two consecutive bytes. The following example shows the arrangement for GM1 GDAT1 (58h–59h). This
arrangement is applicable for all the EEPROM data for all gamma channels.
GDATx Register: EEPROM Data for the Gamma Channels
FACTORY DEFAULT
8000h
MEMORY TYPE
NV
58h
GDAT[9]
GDAT[8]
GDAT[7]
GDAT[6]
GDAT[5]
GDAT[4]
GDAT[3]
GDAT[2]
59h
GDAT[1]
GDAT[0]
x
BIT 7
BIT 0
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