- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376976 > DS3253N Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs PDF資料下載
參數(shù)資料
| 型號： | DS3253N |
| 英文描述： | Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs |
| 中文描述： | 單/雙/三/四DS3/E3/STS-1柳斯 |
| 文件頁數(shù)： | 20/71頁 |
| 文件大小： | 925K |
| 代理商： | DS3253N |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁當前第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁
DS3251/DS3252/DS3253/DS3254
20 of 71
Register Name:
Register Description:
Register Address:
Bit
Name
Default
Bit 7: Jitter Attenuator Full Latched (JAFL).
This latched status bit is set to one when the jitter attenuator buffer
is full. JAFL is cleared when the host processor writes a one to it and is not set again until the full condition clears
and the buffer becomes full again. When JAFL is set, it can cause a hardware interrupt to occur if the JAFIE
interrupt-enable bit in the
SRIE
register is set to one. The interrupt is cleared when JAFL is cleared or JAFIE is set
to zero.
Bit 6: Jitter Attenuator Empty Latched (JAEL).
This latched status bit is set to one when the jitter attenuator
buffer is empty. JAEL is cleared when the host processor writes a one to it and is not set again until the empty
condition clears and the buffer becomes empty again. When JAEL is set, it can cause a hardware interrupt to occur
if the JAEIE interrupt-enable bit in the
SRIE
register is set to one. The interrupt is cleared when JAEL is cleared or
JAEIE is set to zero.
Bit 5: Transmitter Driver Monitor Latched (TDML).
This latched status bit is set to one when the TDM status bit
changes state (low to high or high to low). TDML is cleared when the host processor writes a one to it and is not set
again until TDM changes state again. When TDML is set, it can cause a hardware interrupt to occur if the TDMIE
interrupt-enable bit in the
SRIE
register is set to one. The interrupt is cleared when TDML is cleared or TDMIE is
set to zero.
Bit 4: PRBS Detector Output Latched (PRBSL).
This latched status bit is set to one when the PRBS status bit
changes state (low to high or high to low). PRBSL is cleared when the host processor writes a one to it and is not
set again until PRBS changes state again. When PRBSL is set, it can cause a hardware interrupt to occur if the
PRBSIE interrupt-enable bit in the
SRIE
register is set to one. The interrupt is cleared when PRBSL is cleared or
PRBSIE is set to zero.
Bit 3: PRBS Detector Bit Error Latched (PBERL).
This latched status bit is set to one when the PRBS detector is
in sync and a bit error has been detected. PBERL is cleared when the host processor writes a one to it and is not
set again until another bit error is detected. When PBERL is set, it can cause a hardware interrupt to occur if the
PBERIE interrupt-enable bit in the
SRIE
register is set to one. The interrupt is cleared when PBERL is cleared or
PBERIE is set to zero.
Bit 2: Receiver Code Violation Latched (RCVL).
This latched status bit is set to one when the RCV status bit in
the
SR
register goes high. RCVL is cleared when the host processor writes a one to it and is not set again until
RCV goes high again. When RCVL is set, it can cause a hardware interrupt to occur if the RCVIE interrupt-enable
bit in the
SRIE
register is set to one. The interrupt is cleared when RCVL is cleared or RCVIE is set to zero.
Bit 1: Receiver Loss-of-Clock Lock Latched (RLOLL).
This latched status bit is set to one when the RLOL status
bit in the
SR
register changes state (low to high or high to low). RLOLL is cleared when the host processor writes a
one to it and is not set again until RLOL changes state again. When RLOLL is set, it can cause a hardware
interrupt to occur if the RLOLIE interrupt-enable bit in the
SRIE
register is set to one. The interrupt is cleared when
RLOLL is cleared or RLOLIE is set to zero.
Bit 0: Receiver Loss-of-Signal Latched (RLOSL).
This latched status bit is set to one when the RLOS status bit
in the
SR
register changes state (low to high or high to low). RLOSL is cleared when the host processor writes a
one to it and is not set again until RLOS changes state again. When RLOSL is set, it can cause a hardware
interrupt to occur if the RLOSIE interrupt-enable bit in the
SRIE
register is set to one. The interrupt is cleared when
RLOSL is cleared or RLOSIE is set to zero.
SRLn
Status Register Latched
04h, 14h, 24h, 34h
7
6
5
4
3
2
1
0
JAFL
0
JAEL
0
TDML
0
PRBSL
0
PBERL
0
RCVL
0
RLOLL
0
RLOSL
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS3254 | Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs |
| DS3254N | Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs |
| DS327PIN | Industrial Control IC |
| DSS327 | Industrial Control IC |
| DS328PIN | Analog IC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS3253N# | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Triple DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3253N+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Triple DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3253NA3 | 制造商:Maxim Integrated Products 功能描述:DS3253 REV A3 - Rail/Tube |
| DS3254 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3254+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。