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| 型號(hào)： | DS31256 |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 97/183頁 |
| 文件大小： | 0K |
| 描述： | IC CTRLR HDLC 256-CHANNEL 256BGA |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 控制器類型： | HDLC 控制器 |
| 接口： | 串行 |
| 電源電壓： | 3 V ~ 3.6 V |
| 電流 - 電源： | 500mA |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-BBGA |
| 供應(yīng)商設(shè)備封裝： | 256-BGA（27x27） |
| 包裝： | 管件 |
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DS31256 256-Channel, High-Throughput HDLC Controller
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information about the device through these signals. Only the 16-bit bus width is allowed (i.e., byte addressing is
not available).
Signal Name:
LA0 to LA19
Signal Description:
Local Bus Nonmultiplexed Address Bus
Signal Type:
Input/Output (tri-state capable)
In the PCI bridge mode (LMS = 0), these signals are outputs that are asserted on the rising edge of LCLK to
indicate which address to be written to or read from. These signals are tri-stated when the local bus is not currently
involved in a bus transaction and driven when a bus transaction is active. In configuration mode
(LMS = 1), these signals are inputs and only the bottom 16 (LA[15:0]) are active. The upper four (LA[19:16]) are
ignored and should be connected low.
Signal Name:
LWR (LR/W)
Signal Description:
Local Bus Write Enable (Local Bus Read/Write Select)
Signal Type:
Input/Output (tri-state capable)
In the PCI bridge mode (LMS = 0), this output signal is asserted on the rising edge of LCLK. In Intel mode
(LIM = 0), it is asserted when data is to be written to the local bus. In Motorola mode (LIM = 1), this signal
determines whether a read or write is to occur. If bus arbitration is enabled through the LARBE control bit in the
LBBMC register, this signal is tri-stated when the local bus is not currently involved in a bus transaction and
driven when a bus transaction is active. When bus arbitration is disabled, this signal is always driven. In Intel
mode (LIM = 0), it determines when data is to be written to the device. In Motorola mode (LIM = 1), this signal
determines whether a read or write is to occur.
Signal Name:
LRD (LDS)
Signal Description:
Local Bus Read Enable (Local Bus Data Strobe)
Signal Type:
Input/Output (tri-state capable)
In the PCI bridge mode (LMS = 0), this active-low output signal is asserted on the rising edge of LCLK. In Intel
mode (LIM = 0), it is asserted when data is to be read from the local bus. In Motorola mode (LIM = 1), the rising
edge is used to write data into the slave device. If bus arbitration is enabled through the LARBE control bit in the
LBBMC register, this signal is tri-stated when the local bus is not currently involved in a bus transaction and
driven when a bus transaction is active. When bus arbitration is disabled, this signal is always driven. In Intel
mode (LIM = 0), it determines when data is to be read from the device. In Motorola mode (LIM = 1), the rising
edge writes data into the device.
Signal Name:
LINT
Signal Description:
Local Bus Interrupt
Signal Type:
Input/Output (open drain)
In the PCI bridge mode (LMS = 0), this active-low signal is an input that is sampled on the rising edge of LCLK.
If asserted and unmasked, this signal causes an interrupt at the PCI bus through the
PINTA signal. If not used in
PCI bridge mode, this signal should be connected high. In configuration mode (LMS = 1), this signal is an open-
drain output that is forced low if one or more unmasked interrupt sources within the device is active. The signal
remains low until either the interrupt is serviced or masked.
Signal Name:
LRDY
Signal Description:
Local Bus PCI Bridge Ready (PCI Bridge Mode Only)
Signal Type:
Input
This active-low signal is sampled on the rising edge of LCLK to determine when a bus transaction is complete.
This signal is only examined when a bus transaction is taking place. This signal is ignored when the local bus is in
configuration mode (LMS = 1) and should be connected high.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS31256+ | 功能描述:輸入/輸出控制器接口集成電路 256Ch High Thruput HDLC Cntlr RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| DS31256B | 功能描述:輸入/輸出控制器接口集成電路 256Ch High Thruput HDLC Cntlr RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| DS31256DK | 功能描述:網(wǎng)絡(luò)開發(fā)工具 RoHS:否 制造商:Rabbit Semiconductor 產(chǎn)品:Development Kits 類型:Ethernet to Wi-Fi Bridges 工具用于評(píng)估:RCM6600W 數(shù)據(jù)速率:20 Mbps, 40 Mbps 接口類型:802.11 b/g, Ethernet 工作電源電壓:3.3 V |
| DS31256-W+ | 制造商:Maxim Integrated Products 功能描述:ENVOY 256 CHANNEL HDLC - WAIVER - Rail/Tube |
| DS312BNC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Industrial Control IC |
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