參數(shù)資料
型號(hào): DS31256
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 111/183頁(yè)
文件大?。?/td> 0K
描述: IC CTRLR HDLC 256-CHANNEL 256BGA
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 40
控制器類(lèi)型: HDLC 控制器
接口: 串行
電源電壓: 3 V ~ 3.6 V
電流 - 電源: 500mA
工作溫度: 0°C ~ 70°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 256-BBGA
供應(yīng)商設(shè)備封裝: 256-BGA(27x27)
包裝: 管件
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)當(dāng)前第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)
DS31256 256-Channel, High-Throughput HDLC Controller
33 of 183
Bit 0/Receive DMA Enable (RDE). This bit is used to enable the receive DMA. When it is set to 0, the receive
DMA does not pass any data from the receive FIFO to the PCI bus, even if one or more HDLC channels is
enabled. On device initialization, the host should fully configure the receive DMA before enabling it through this
bit.
0 = receive DMA is disabled
1 = receive DMA is enabled
Bit 1/Receive DMA Throttle Select Bit 0 (RDT0); Bit 2/Receive DMA Throttle Select Bit 1 (RDT1). These
two bits select the maximum burst length that the receive DMA is allowed on the PCI bus. The DMA can be
restricted to a maximum burst length of just 32 dwords (128 Bytes) or it can be incrementally adjusted up to 256
dwords (1024 Bytes). The host selects the optimal length based on a number of factors, including the system
environment for the PCI bus, the number of HDLC channels being used, and the trade-off between channel latency
and bus efficiency.
00 = burst length maximum is 32 dwords
01 = burst length maximum is 64 dwords
10 = burst length maximum is 128 dwords
11 = burst length maximum is 256 dwords
Bit 3/Transmit DMA Enable (TDE). This bit is used to enable the transmit DMA. When it is set to 0, the
transmit DMA does not pass any data from the PCI bus to the transmit FIFO, even if one or more HDLC channels
is enabled. On device initialization, the host should fully configure the transmit DMA before enabling it through
this bit.
0 = transmit DMA is disabled
1 = transmit DMA is enabled
Bit 4/Transmit DMA Throttle Select Bit 0 (TDT0); Bit 5/Transmit DMA Throttle Select Bit 1 (TDT1). These
two bits select the maximum burst length the transmit DMA is allowed on the PCI bus. The DMA can be restricted
to a maximum burst length of just 32 dwords (128 Bytes) or it can be incrementally adjusted up to 256 dwords
(1024 Bytes). The host selects the optimal length based on a number of factors, including the system environment
for the PCI bus, the number of HDLC channels being used, and the trade-off between channel latency and bus
efficiency.
00 = burst length maximum is 32 dwords
01 = burst length maximum is 64 dwords
10 = burst length maximum is 128 dwords
11 = burst length maximum is 256 dwords
Bit 6/PCI Bus Orientation (PBO). This bit selects whether HDLC packet data on the PCI bus operates in either
Little Endian or Big Endian format. Little Endian byte ordering places the least significant byte at the lowest
address, while Big Endian places the least significant byte at the highest address. This bit setting only affects
HDLC data on the PCI bus. All other PCI bus transactions to the internal device configuration registers, PCI
configuration registers, and local bus are always in Little Endian format.
0 = HDLC packet data on the PCI bus is in Little Endian format
1 = HDLC packet data on the PCI bus is in Big Endian format
相關(guān)PDF資料
PDF描述
DS3112N IC MUX TEMPE T3/E3 IND 256-BGA
CONREVSMA002-SMD CONN RP-SMA FEMALE R-A SMD
DS21FT44N IC FRAMER E1 4X3 12CH IND 300BGA
PIC16F1933-E/SP MCU 8BIT 4K FLASH 28-DIP
DS21FF42+ IC FRAMER T1 4X4 16CH 300-BGA
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS31256+ 功能描述:輸入/輸出控制器接口集成電路 256Ch High Thruput HDLC Cntlr RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray
DS31256B 功能描述:輸入/輸出控制器接口集成電路 256Ch High Thruput HDLC Cntlr RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray
DS31256DK 功能描述:網(wǎng)絡(luò)開(kāi)發(fā)工具 RoHS:否 制造商:Rabbit Semiconductor 產(chǎn)品:Development Kits 類(lèi)型:Ethernet to Wi-Fi Bridges 工具用于評(píng)估:RCM6600W 數(shù)據(jù)速率:20 Mbps, 40 Mbps 接口類(lèi)型:802.11 b/g, Ethernet 工作電源電壓:3.3 V
DS31256-W+ 制造商:Maxim Integrated Products 功能描述:ENVOY 256 CHANNEL HDLC - WAIVER - Rail/Tube
DS312BNC 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Industrial Control IC