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參數(shù)資料
| 型號(hào)： | DS26518GNB1+ |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 272/312頁(yè) |
| 文件大小： | 0K |
| 描述： | IC TXRX T1/E1/J1 8PRT 256-CSBGA |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 類型： | 收發(fā)器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 8/8 |
| 規(guī)程： | T1/E1/J1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-BGA，CSBGA |
| 供應(yīng)商設(shè)備封裝： | 256-CSBGA（17x17） |
| 包裝： | 管件 |
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DS26518 8-Port T1/E1/J1 Transceiver
62 of 312
9.9.6.1 Additional E1 Receive Sa- and Si-Bit Receive Operation (E1 Mode)
The DS26518, when operated in the E1 mode, provides for access to both the Sa and the Si bits via two methods.
The first involves using the internal E1RAF/E1RNAF and E1TAF/E1TNAF registers. The second method involves
an expanded version of the first method.
9.9.6.1.1 Internal Register Scheme Based on Double-Frame (Method 1)
On the receive side, the E1RAF and E1RNAF registers will always report the data as it received in the Sa and Si bit
locations. The E1RAFand E1RNAF registers are updated on align frame boundaries. The setting of the Receive
Align Frame bit in Receive Latched Status Register 2 (RLS2.0) will indicate that the contents of the RAF and RNAF
have been updated. The host can use the RLS2.0 bit to know when to read the E1RAF and E1RNAF registers. The
host has 250
μs to retrieve the data before it is lost.
9.9.6.1.2 Internal Register Scheme Based on CRC-4 Multiframe (Receive)
On the receive side, there is a set of eight registers (E1RsiAF, E1RSiNAF, E1RRA, E1RSa4 to E1RSa8) that report
the Si and Sa bits as they are received. These registers are updated with the setting of the receive CRC-4
multiframe bit in Receive Latched Status Register 2 (RLS2.1). The host can use the RLS2.1 bit to know when to
read these registers. The user has 2ms to retrieve the data before it is lost. See the register descriptions for
additional information.
9.9.6.1.3 Internal Register Scheme Based on CRC-4 Multiframe (Transmit)
On the transmit side there is a set of eight registers (E1TSiAF, E1TSiNAF, E1TRA, E1TSa4 to E1TSa8) that, via
the E1 Transmit Sa-Bit Control Register (E1TSACR), can be programmed to insert both Si and Sa data. Data is
sampled from these registers with the setting of the transmit multiframe bit in Transmit Latched Status Register 1
(TLS1.3). The host can use the TLS1.3 bit to know when to update these registers. It has 2ms to update the data or
else the old data will be retransmitted. See the register descriptions in Section 10 for more information.
9.9.6.2 Sa-Bit Monitoring and Reporting
In addition to the registers outlined above, the DS26518 provides status and interrupt capability in order to detect
changes in the state of selected Sa bits. The E1RSAIMR register can be used to select which Sa bits are
monitored for a change of state. When a change of state is detected in one of the enabled Sa bit positions, a status
bit is set in the
9
RLS7 register via the SaXCD bit (bit 0). This status bit can in turn be used to generate an interrupt
by unmasking RIM7.0 (SaXCD). If multiple Sa bits have been enabled, the user can read the SaBITS register at
address 06Eh to determine the current value of each Sa bit.
For the Sa6 bits, additional support is available to detect specific codewords per ETS 300 233. The Sa6CODE
register will report the received Sa6 codeword. The codeword must be stable for a period of three submultiframes
and be different from the previous stored value in order to be updated in this register. See the
description for further details on the operation of this register and the values reported in it. An additional status bit is
provided in
RLS7.1 (Sa6CD) to indicate if the received Sa6 codeword has changed. A mask bit is provided for this
status bit in
9
RIM7 to allow for interrupt generation when enabled.
9.9.7 Maintenance and Alarms
The DS26518 provides extensive functions for alarm detection and generation. It also provides diagnostic functions
for monitoring of performance and sending of diagnostic information:
Real-time and latched status bits, interrupts and interrupt mask for transmitter and receiver
LOS detection
RIA detection and generation
Error counters
DS0 monitoring
Milliwatt generation and detection
Slip buffer status for transmit and receive
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS26518GNB1+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 8-Port E1/T1/J1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS26518NB1+ | 功能描述:IC TXRX T1/E1/J1 8PORT 256-CSBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:25 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:4.5 V ~ 5.5 V 安裝類型:通孔 封裝/外殼:16-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:16-PDIP 包裝:管件 |
| DS26519 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:16-Port T1/E1/J1 Transceiver |
| DS26519DK | 功能描述:網(wǎng)絡(luò)開發(fā)工具 DS26519 Dev Kit RoHS:否 制造商:Rabbit Semiconductor 產(chǎn)品:Development Kits 類型:Ethernet to Wi-Fi Bridges 工具用于評(píng)估:RCM6600W 數(shù)據(jù)速率:20 Mbps, 40 Mbps 接口類型:802.11 b/g, Ethernet 工作電源電壓:3.3 V |
| DS26519G | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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