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| 型號(hào)： | DS26518GNB1+ |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 244/312頁(yè) |
| 文件大小： | 0K |
| 描述： | IC TXRX T1/E1/J1 8PRT 256-CSBGA |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 類型： | 收發(fā)器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 8/8 |
| 規(guī)程： | T1/E1/J1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-BGA，CSBGA |
| 供應(yīng)商設(shè)備封裝： | 256-CSBGA（17x17） |
| 包裝： | 管件 |
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DS26518 8-Port T1/E1/J1 Transceiver
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9.8.1.1 Elastic Stores Initialization
There are two elastic store initializations that may be used to improve performance in certain applications: elastic
store reset and elastic store align. Both of these involve the manipulation of the elastic store’s read and write
pointers and are useful primarily in synchronous applications (RSYSCLKn/TSYSCLKn are locked to
RCLKn/TCLKn, respectively). The elastic store reset is used to minimize the delay through the elastic store. The
elastic store align bit is used to center the read/write pointers to the extent possible.
Table 9-4. Elastic Store Delay After Initialization
INITIALIZATION
REGISTER BIT
DELAY
Receive Elastic Store Reset
RESCR.2
N bytes < Delay < 1 Frame + N bytes
Transmit Elastic Store Reset
TESCR.2
N bytes < Delay < 1 Frame + N bytes
Receive Elastic Store Align
RESCR.3
1/2 Frame < Delay < 1 1/2 Frames
Transmit Elastic Store Align
TESCR.3
1/2 Frame < Delay < 1 1/2 Frames
N = 9 for RSZS = 0; N = 2 for RSZS = 1
9.8.1.2 Minimum Delay Mode
Elastic store minimum delay mode may be used when the elastic store’s system clock is locked to its network clock
(i.e., RCLKn locked to RSYSCLKn for the receive side and TCLKn locked to TSYSCLKn for the transmit side).
RESCR.1 enables the receive elastic store minimum delay mode. When enabled, the elastic stores will be forced to
a maximum depth of 32 bits instead of the normal two-frame depth. This feature is useful primarily in applications
that interface to a 2.048MHz bus. Certain restrictions apply when minimum delay mode is used. In addition to the
restriction mentioned above, RSYNCn must be configured as an output when the receive elastic store is in
minimum delay mode, and TSYNCn must be configured as an output when transmit minimum delay mode is
enabled. In this mode, the SYNC outputs are always in frame mode (multiframe outputs are not allowed). In a
typical application RSYSCLKn and TSYSCLKn are locked to RCLKn, and RSYNCn (frame output mode) is
connected to TSSYNCIOn (frame input mode). The slip zone select bit (RSZS at RESCR.4) must be set to 1. All
the slip contention logic in the framer is disabled (since slips cannot occur). On power-up after the RSYSCLKn and
TSYSCLKn signals have locked to their respective network clock signals, the elastic store reset bit (RESCR.2)
should be toggled from a zero to a one to ensure proper operation.
9.8.1.3 Additional Receive Elastic Store Information
If the receive-side elastic store is enabled, then the user must provide either a 1.544MHz or 2.048MHz clock at the
RSYSCLKn pin. See Section 9.8.2 for higher rate system clock applications. The user has the option of either
providing a frame/multiframe sync at the RSYNCn pin or having the RSYNCn pin provide a pulse on
frame/multiframe boundaries. If signaling reinsertion is enabled, the robbed-bit signaling data is realigned to the
multiframe sync input on RSYNCn. Otherwise, a multiframe sync input on RSYNCn is treated as a simple frame
boundary by the elastic store. The framer will always indicate frame boundaries on the network side of the elastic
store via the RFSYNCn output whether the elastic store is enabled or not. Multiframe boundaries will always be
indicated via the RMSYNCn output. If the elastic store is enabled, then RMSYNCn will output the multiframe
boundary on the backplane side of the elastic store. When the device is receiving T1 and the backplane is enabled
for 2.048MHz operation, the RMSYNCn signal will output the T1 multiframe boundaries as delayed through the
elastic store. When the device is receiving E1 and the backplane is enabled for 1.544MHz operation, the
RMSYNCn signal will output the E1 multiframe boundaries as delayed through the elastic store.
If the user selects to apply a 2.048MHz clock to the RSYSCLKn pin, the user can use the backplane blank channel
select registers (RBCS1–4) to determine which channels will have the data output at RSERn forced to all ones.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| DS26518GNB1+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 8-Port E1/T1/J1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS26518NB1+ | 功能描述:IC TXRX T1/E1/J1 8PORT 256-CSBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:25 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:4.5 V ~ 5.5 V 安裝類型:通孔 封裝/外殼:16-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:16-PDIP 包裝:管件 |
| DS26519 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:16-Port T1/E1/J1 Transceiver |
| DS26519DK | 功能描述:網(wǎng)絡(luò)開發(fā)工具 DS26519 Dev Kit RoHS:否 制造商:Rabbit Semiconductor 產(chǎn)品:Development Kits 類型:Ethernet to Wi-Fi Bridges 工具用于評(píng)估:RCM6600W 數(shù)據(jù)速率:20 Mbps, 40 Mbps 接口類型:802.11 b/g, Ethernet 工作電源電壓:3.3 V |
| DS26519G | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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