參數(shù)資料
型號： DS26303LN-120+
廠商： Maxim Integrated Products
文件頁數(shù)： 41/101頁
文件大小： 0K
描述： IC LIU E1/T1/J1 3.3V 144-ELQFP
產(chǎn)品培訓模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 13
類型： 線路接口裝置（LIU）
驅動器/接收器數(shù)： 8/8
規(guī)程： T1/E1/J1
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 144-LQFP 裸露焊盤
供應商設備封裝： 144-LQFP 裸露焊盤
包裝： 托盤
產(chǎn)品目錄頁面： 1430 (CN2011-ZH PDF)
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
44 of 101
Register Name:
LVDS
Register Description:
Line Violation Detect Status Register
Register Address:
12h
Bit #
7
6
5
4
3
2
1
0
Name
LVDS8
LVDS7
LVDS6
LVDS5
LVDS4
LVDS3
LVDS2
LVDS1
Default
0
Bits 7 to 0: Line Violation Detect Status n (LVDSn).
A bipolar violation, code violation, or excessive zeros cause
the associated LVDSn bit to latch. This bit is cleared on a read operationif GISC.CWE is reset. This bit is cleared
by a write operation to the bit if GISC.CWE is set. The LVDS register captures the first violation within a three-
clock-period window. If a second violation occurs after the first violation within the three-clock-period window, then
the second violation will not be latched even if a read to the LVDS register was performed. Excessive zeros need to
be enabled by the EZDE register for detection by this register. Code violations are only relative when in HDB3
mode and can be disabled for detection by this register by setting the CVDEB register. In dual-rail mode only
bipolar violations are relevant for this register.
Register Name:
RCLKI
Register Description:
Receive Clock Invert Register
Register Address:
13h
Bit #
7
6
5
4
3
2
1
0
Name
RCLKI8
RCLKI7
RCLKI6
RCLKI5
RCLKI4
RCLKI3
RCLKI2
RCLKI1
Default
0
Bits 7 to 0: Receive Clock Invert n (RCLKIn).
When this bit is set the RCLKn is inverted. This aligns
RPOSn/RNEGn on the falling edge of RCLKn. When reset, RPOSn/RNEGn is aligned on the rising edge of
RCLKn. Note that if the CLKE pin is high, the RPOSn/RNEGn is set on the falling edge of RCLKn regardless of the
settings in this register.
Register Name:
TCLKI
Register Description:
Transmit Clock Invert Register
Register Address:
14h
Bit #
7
6
5
4
3
2
1
0
Name
TCLKI8
TCLKI7
TCLKI6
TCLKI5
TCLKI4
TCLKI3
TCLKI2
TCLKI1
Default
0
Bits 7 to 0: Transmit Clock Invert n (TCLKIn).
When this bit is set the TCLKn is inverted. TPOSn/TNEGn should
be aligned on the rising edge of TCLKn. When reset, TPOSn/TNEGn should be aligned on the falling edge of
TCLKn.
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相關代理商/技術參數(shù)
參數(shù)描述
DS26303LN-120+ 功能描述:電信線路管理 IC 3.3V E1/T1/J1 Short Haul Octal LIU RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
DS26303LN-120+A3 功能描述:電信線路管理 IC 3.3V E1/T1/J1 Short Haul Octal LIU RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
DS26303LN-120A3 功能描述:電信線路管理 IC 3.3V E1/T1/J1 Short Haul Octal LIU RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
DS26303LN-75 功能描述:電信線路管理 IC 3.3V E1/T1/J1 Short Haul Octal LIU RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
DS26303LN-75+ 功能描述:電信線路管理 IC 3.3V E1/T1/J1 Short Haul Octal LIU RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
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