參數(shù)資料
型號(hào)： DS26303GN-120
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： 數(shù)字傳輸電路
英文描述： 3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit
中文描述： DATACOM, PCM TRANSCEIVER, PBGA160
封裝： PLASTIC, BGA-160
文件頁數(shù)： 42/97頁
文件大?。?/td> 966K
代理商： DS26303GN-120
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
42 of 97
Register Name:
Register Description:
Register Address:
Bit #
Name
BTCR
Bit Error-Rate Tester Control Register
10h
7
6
5
4
—
3
2
—
0
1
—
0
0
BTS2
BTS1
BTS0
—
BERTE
Default
Bits 7 to 5: Bit Error-Rate Transceiver Select [2:0] (BTS[2:0]).
These bits BTS[2:0] select the LIU that the BERT
applies to. This is only applicable if the BERTE bit is set.
0
0
0
0
0
0
Bit 0: Bit Error-Rate Tester Enable (BERTE).
When this bit is set, the BERT is enabled. The BERT is only active
for one transceiver at a time selected by BTS[2:0].
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: BPV Error Insertion Register
n
(BEIR
n
).
A 0-to-1 transition on this bit causes a single bipolar
violation (BPV) to be inserted into the transmit data stream channel
n
. This bit must be cleared and set again for a
subsequent error to be inserted.
BEIR
BPV Error Insertion Register
11h
7
6
5
4
3
2
1
0
BEIR8
0
BEIR7
0
BEIR6
0
BEIR5
0
BEIR4
0
BEIR3
0
BEIR2
0
BEIR1
0
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: Line Violation Detect Status
n
(LVDS
n
).
A bipolar violation, code violation, or excessive zeros cause
the associated LVDS
n
bit to latch. This bit is cleared on a read operation. The LVDS register captures the first
violation within a three-clock-period window. If a second violation occurs after the first violation within the three-
clock-period window, then the second violation will not be latched even if a read to the LVDS register was
performed. Excessive zeros need to be enabled by the
EZDE
register for detection by this register. Code violations
are only relative when in HDB3 mode and can be disabled for detection by this register by setting the
CVDEB
register. In dual-rail mode only bipolar violations are relevant for this register.
LVDS
Line Violation Detect Status
12h
7
6
5
4
3
2
1
0
LVDS8
0
LVDS7
0
LVDS6
0
LVDS5
0
LVDS4
0
LVDS3
0
LVDS2
0
LVDS1
0
相關(guān)PDF資料
PDF描述
DS26303GN-75 3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit
DS26303L-120 3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit
DS26303L-75 3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit
DS26303LN-120 3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit
DS26303LN-75 3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS26303GN-75 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit
DS26303L-120 功能描述:電信線路管理 IC 3.3V E1/T1/J1 Short Haul Octal LIU RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
DS26303L-120+ 功能描述:電信線路管理 IC 3.3V E1/T1/J1 Short Haul Octal LIU RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
DS26303L-120+A3 功能描述:電信線路管理 IC 3.3V E1/T1/J1 Short Haul Octal LIU RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
DS26303L-120A3 功能描述:電信線路管理 IC 3.3V E1/T1/J1 Short Haul Octal LIU RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
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