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參數(shù)資料
| 型號(hào)： | DS26303GN-120 |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | 3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit |
| 中文描述： | DATACOM, PCM TRANSCEIVER, PBGA160 |
| 封裝： | PLASTIC, BGA-160 |
| 文件頁數(shù)： | 41/97頁 |
| 文件大?。?/td> | 966K |
| 代理商： | DS26303GN-120 |
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DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
41 of 97
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 6: PLL Clock Input (PCLKI).
This bit selects the input into to the PLL.
0 = MCLK is used.
1 = RCLK1–RCLK8 is used based on the selection in register
CCR
.
Bit 5: T1/E1 Clock Enable (TECLKE).
When this bit is set the TECLK output is enabled. If not set TECLK is
disabled and the TECLK output is an RLOS output. TECLK requires PLLE to be set for correct functionality.
MC
Master Clock Select
06h
7
—
0
6
5
4
3
2
1
0
PCLKI
0
TECLKE
0
CLKAE
0
MPS1
0
MPS0
0
FREQS
0
PLLE
0
Bit 4: Clock A Enable (CLKAE).
When this bit is set the CLKA output is enabled. If not set CLKA is disabled to tri-
state. CLKA requires PLLE to be set for correct functionality.
Bits 3 to 2: Master Period Select [1:0] (MPS[1:0]).
These bits MPS[1:0] selects the external MCLK frequency for
the DS26303. See
Table 5-13
for details.
Bit 1: Frequency Select (FREQS).
In conjunction with MPS[1:0], this bit selects the external MCLK frequency for
the DS26303. If this bit is set the external master clock can be 1.544MHz or a multiple thereof. If not set the
external master clock can be 2.048MHz or a multiple thereof. See
Table 5-13
for details.
Bit 0: Phase Lock Loop Enable (PLLE).
When this bit is set the phase lock loop is enabled. If not set MCLK is the
applied input clock.
Table 5-13. MCLK Selections
PLLE
MPS1, MPS0
MCLK
(MHz/±50ppm)
1.544
2.048
1.544
3.088
6.176
12.352
2.048
4.096
8.192
16.384
FREQS
MODE
0
0
1
1
1
1
1
1
1
1
xx
xx
00
01
10
11
00
01
10
11
x
x
1
1
1
1
0
0
0
0
T1
E1
T1/J1 or E1
T1/J1 or E1
T1/J1 or E1
T1/J1 or E1
T1/J1 or E1
T1/J1 or E1
T1/J1 or E1
T1/J1 or E1
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0: Receive Hitless-Protection Mode Control (RHPMC).
This bit when set and, when the OE pin goes low, will
force all the receivers to turn off any internal impedance matching on RTIP and RRING. This is used for hitless-
protection switching when the user would like a system requiring no external relays in the system.
GMR
Global Management Register
07h
7
—
0
6
—
0
5
—
0
4
—
0
3
—
0
2
—
0
1
—
0
0
RHPMC
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS26303GN-75 | 3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit |
| DS26303L-120 | 3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit |
| DS26303L-75 | 3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit |
| DS26303LN-120 | 3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit |
| DS26303LN-75 | 3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS26303GN-75 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit |
| DS26303L-120 | 功能描述:電信線路管理 IC 3.3V E1/T1/J1 Short Haul Octal LIU RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| DS26303L-120+ | 功能描述:電信線路管理 IC 3.3V E1/T1/J1 Short Haul Octal LIU RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| DS26303L-120+A3 | 功能描述:電信線路管理 IC 3.3V E1/T1/J1 Short Haul Octal LIU RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| DS26303L-120A3 | 功能描述:電信線路管理 IC 3.3V E1/T1/J1 Short Haul Octal LIU RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
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