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參數(shù)資料
| 型號： | DS2506 |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | DRAM |
| 英文描述： | 64K bit Add-Only Memory(64K位只加存儲器) |
| 中文描述： | 64K X 1 OTPROM, PBCY3 |
| 封裝： | PR-35, 3 PIN |
| 文件頁數(shù)： | 18/24頁 |
| 文件大?。?/td> | 148K |
| 代理商： | DS2506 |
DS2506
052298 18/24
Overdrive Skip ROM [3CH]
On a single–drop bus this command can save time by
allowing the bus master to access the memory functions
without providing the 64–bit ROM code. Unlike the normal
Skip ROM command the Overdrive Skip ROM sets the
DS2506 in the Overdrive Mode (OD=1). All communica-
tion following this command has to occur at Overdrive
Speed until a reset pulse of minimum 480
μ
s duration
resets all devices on the bus to regular speed (OD=0).
When issued on a multidrop bus this command will set
all Overdrive–capable devices into Overdrive mode. To
subsequently address a specific Overdrive–capable
device, a reset pulse at Overdrive speed has to be
issued followed by a Match ROM or Search ROM com-
mand sequence. This will shorten the time for the
search process. If more than one slave supporting
Overdrive is present on the bus and the Overdrive Skip
ROM command is followed by a read command, data
collision will occur on the bus as multiple slaves transmit
simultaneously (open drain pull–downs will produce a
wire–AND result).
Overdrive Match ROM [69H}
The Overdrive Match ROM command, followed by a
64–bit ROM sequence transmitted at Overdrive Speed,
allows the bus master to address a specific DS2506 on
a multidrop bus and to simultaneously set it in Overdrive
Mode. Only the DS2506 that exactly matches the 64–bit
ROM sequence will respond to the subsequent memory
function command. Slaves already in Overdrive mode
from a previous Overdrive Skip or Match command will
remain in Overdrive mode. All other slaves that do not
match the 64–bit ROM sequence or do not support
Overdrive will return to or remain at regular speed and
wait for a reset pulse of minimum 480
μ
s duration. The
Overdrive Match ROM command can be used with a
single or multiple devices on the bus.
1–Wire Signalling
The DS2506 requires strict protocols to insure data
integrity. The protocol consists of five types of signaling
on one line: Reset Sequence with Reset Pulse and
Presence Pulse, Write 0, Write 1, Read Data and Pro-
gram Pulse. All these signals except presence pulse are
initiated by the bus master. The DS2506 can communi-
cate at two different speeds, regular speed and Over-
drive Speed. If not explicitly set into the Overdrive Mode,
the DS2506 will communicate at regular speed. While in
Overdrive Mode the fast timing applies to all commu-
nication–related wave forms.
The initialization sequence required to begin any com-
munication with the DS2506 is shown in Figure 9. A
Reset Pulse followed by a Presence Pulse indicates the
DS2506 is ready to accept a ROM command. The bus
master transmits (TX) a reset pulse (t
RSTL
, minimum
480
μ
s at regular speed, 48
μ
s at Overdrive Speed). The
bus master then releases the line and goes into receive
mode (RX). The 1–Wire bus is pulled to a high state via
the pull–up resistor. After detecting the rising edge on
the data pin, the DS2506 waits (t
PDH
, 15–60
μ
s at regu-
lar speed, 2–6
μ
s at overdrive speed) and then transmits
the presence pulse (t
PDL
, 60–240
μ
s at regular speed,
8–24
μ
s at Overdrive Speed).
A Reset Pulse of 480
μ
s or longer will exit the Overdrive
Mode returning the device to regular speed. If the DS2506
is in Overdrive Mode and the Reset Pulse is no longer
than 80
μ
s the device will remain in Overdrive Mode.
Read/Write Time Slots
The definitions of write and read time slots are illustrated
in Figure 10. All time slots are initiated by the master
driving the data line low. The falling edge of the data line
synchronizes the DS2506 to the master by triggering a
delay circuit in the DS2506. During write time slots, the
delay circuit determines when the DS2506 will sample
the data line. For a read data time slot, if a “0” is to be
transmitted, the delay circuit determines how long the
DS2506 will hold the data line low overriding the 1 gen-
erated by the master. If the data bit is a “1”, the device
will leave the read data time slot unchanged.
PROGRAM PULSE
To copy data from the 8–bit scratchpad to the EPROM
Data or Status Memory, a program pulse of 12 volts is
applied to the data line after the bus master has con-
firmed that the CRC for the current byte is correct. Dur-
ing programming, the bus master controls the transition
from a state where the data line is idling high via the
pull–up resistor to a state where the data line is actively
driven to a programming voltage of 12 volts providing a
minimum of 10 mA of current to the DS2506. This pro-
gramming voltage (Figure 11) should be applied for
480
μ
s, after which the bus master returns the data line
to an idle high state controlled by the pull–up resistor.
Note that due to the high voltage programming require-
ments for any 1–Wire EPROM device, it is not possible
to multi–drop non–EPROM based 1–Wire devices with
the DS2506 during programming. An internal diode
within the non–EPROM based 1–Wire devices will
attempt to clamp the data line at approximately 8 volts
and could potentially damage these devices.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS2506+ | 制造商:Maxim Integrated Products 功能描述:64-KBIT ADD-ONLY MEMORY 3PIN PR35 - Bulk |
| DS2506S | 制造商:Maxim Integrated Products 功能描述:ADD-O MEM 64KB, SOIC8 (GENERIC) - Rail/Tube |
| DS2506S+ | 制造商:Maxim Integrated Products 功能描述:64-KBIT ADD-ONLY MEMORY 8SOIC - Rail/Tube 制造商:Maxim Integrated Products 功能描述:64KB ADD-ONLY MEMORY 制造商:Maxim Integrated Products 功能描述:IC EPROM 64KBIT SMD 2506 SOIC8 |
| DS2506S-UNW | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:UniqueWare Add-Only Memory |
| DS2506S-UNW-PPPP | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:UniqueWare Add-Only Memory |
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