I2
參數(shù)資料
型號： DS2483Q+T
廠商： Maxim Integrated Products
文件頁數(shù)： 13/29頁
文件大?。?/td> 0K
描述： IC I2C TO 1WIRE BRIDGE 8TDFN
產(chǎn)品培訓(xùn)模塊： Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
系列： *
20
Maxim Integrated
DS2483
Single-Channel 1-Wire Master
with Adjustable Timing and Sleep Mode
I2C Definitions
The following terminology is commonly used to describe
I2C data transfers. See Figure 9 for a timing diagram.
Bus Idle or Not Busy: Both SDA and SCL are inac-
tive and in their logic-high states.
START Condition: To initiate communication with a
slave, the master must generate a START condition.
A START condition is defined as a change in state of
SDA from high to low while SCL remains high.
STOP Condition: To end communication with a
slave, the master must generate a STOP condition. A
STOP condition is defined as a change in state of SDA
from low to high while SCL remains high.
Repeated START Condition: Repeated STARTs are
commonly used for read accesses to select a specific
data source or address from which to read. The mas-
ter can use a repeated START condition at the end
of a data transfer to immediately initiate a new data
transfer following the current one. A repeated START
condition is generated the same way as a normal
START condition, but without leaving the bus idle after
a STOP condition.
Data Valid: With the exception of the START and
STOP condition, transitions of SDA can occur only
during the low state of SCL. The data on SDA must
remain valid and unchanged during the entire high
pulse of SCL plus the required setup and hold time
(tHD:DAT after the falling edge of SCL and tSU:DAT
before the rising edge of SCL; see Figure 9). There is
one clock pulse per bit of data. Data is shifted into the
receiving device during the rising edge of SCL pulse.
When finished with writing, the master must release
the SDA line for a sufficient amount of setup time
(minimum tSU:DAT + tR in Figure 9) before the next ris-
ing edge of SCL to start reading. The slave shifts out
each data bit on SDA at the falling edge of the previ-
ous SCL pulse and the data bit is valid at the rising
edge of the current SCL pulse. The master generates
all SCL clock pulses, including those needed to read
from a slave.
Acknowledge: Typically a receiving device, when
addressed, is obliged to generate an acknowledge
after the receipt of each byte. The master must
generate a clock pulse that is associated with this
acknowledge bit. A device that acknowledges must
pull SDA low during the acknowledge clock pulse
in such a way that SDA is stable low during the high
period of the acknowledge-related clock pulse plus
the required setup and hold time (tHD:DAT after the
falling edge of SCL and tSU:DAT before the rising
edge of SCL).
Figure 9. I2C Timing Diagram
SCL
NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN).
SDA
STOP
START
REPEATED
START
SPIKE
SUPPRESSION
tBUF
tHD:STA
tHD:DAT
tSU:DAT
tSU:STO
tHD:STA
tSP
tSU:STA
tHIGH
tR
tF
tLOW
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