參數(shù)資料
型號(hào)： DS2422X
廠商： DALLAS SEMICONDUCTOR
元件分類： Memory IC:Other
英文描述： SPECIALTY MEMORY CIRCUIT, UUC
文件頁(yè)數(shù)： 9/23頁(yè)
文件大?。?/td> 146K
代理商： DS2422X
DS2422/DS2423
021998 17/23
1–WIRE SIGNALING
The DS242X requires strict protocols to insure data
integrity. The protocol consists of four types of signaling
on one line: Reset Sequence with Reset Pulse and
Presence Pulse, Write 0, Write 1 and Read Data. All
these signals except presence pulse are initiated by the
bus master. The DS242X can communicate at two dif-
ferent speeds, regular speed and Overdrive Speed. If
not explicitly set into the Overdrive mode, the DS242X
will communicate at regular speed. While in Overdrive
Mode the fast timing applies to all wave forms.
The initialization sequence required to begin any com-
munication with the DS242X is shown in Figure 10. A
reset pulse followed by a presence pulse indicates the
DS242X is ready to send or receive data given the cor-
rect ROM command and memory function command.
The bus master transmits (TX) a reset pulse (tRSTL,
minimum 480
s at regular speed, 48 s at Overdrive
Speed). The bus master then releases the line and
goes into receive mode (RX). The 1–Wire bus is pulled
to a high state via the pull–up resistor. After detecting
the rising edge on the data pin, the DS242X waits (tPDH,
15–60
s at regular speed, 2–6 s at Overdrive speed)
and then transmits the presence pulse (tPDL, 60–240 s
at regular speed, 8–24
s at Overdrive Speed).
A Reset Pulse of 480
s or longer will exit the Overdrive
Mode returning the device to regular speed.
If the
DS242X is in Overdrive Mode and the Reset Pulse is no
longer than 80
s the device will remain in Overdrive
Mode.
Read/Write Time Slots
The definitions of write and read time slots are illustrated
in Figure 11. All time slots are initiated by the master
driving the data line low. The falling edge of the data line
synchronizes the DS242X to the master by triggering a
delay circuit in the DS242X. During write time slots, the
delay circuit determines when the DS242X will sample
the data line. For a read data time slot, if a “0” is to be
transmitted, the delay circuit determines how long the
DS242X will hold the data line low overriding the 1 gen-
erated by the master. If the data bit is a “1”, the device
will leave the read data time slot unchanged.
INITIALIZATION PROCEDURE “RESET AND PRESENCE PULSES” Figure 10
tRSTH
tRSTL
tR
VPULLUP
VPULLUP MIN
VIH MIN
VIL MAX
0V
Regular Speed
480
s < tRSTL < 1*
480
s < tRSTH < 1**
15
s < tPDH < 60 s
60
s < tPDL < 240 s
tPDH
tPDL
MASTER RX “PRESENCE PULSE”
MASTER TX “RESET PULSE”
RESISTOR
MASTER
DS242X
Overdrive Speed
48
s < tRSTL < 80 s
48
s < tRSTH < 1**
2
s < tPDH < 6 s
8
s < tPDL < 24 s
*IN ORDER NOT TO MASK INTERRUPT SIGNALING BY OTHER DEVICES ON THE 1–WIRE BUS, tRSTL +tR
SHOULD ALWAYS BE LESS THAN 960
s
**INCLUDES RECOVERY TIME
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參數(shù)描述
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