DS2408
28 of 39
Figure 16. CRC-16 HARDWARE DESCRIPTION AND POLYNOMIAL
POLYNOMIAL = X16 + X15 + X2 + 1
X0
X1
X2
X3
X4
X5
X6
X7
X8
X9
X10
X11
X12
X13
X14
X15
X16
1st
STAGE
2nd
STAGE
3rd
STAGE
4th
STAGE
6th
STAGE
5th
STAGE
7th
STAGE
8th
STAGE
9th
STAGE
10th
STAGE
11th
STAGE
12th
STAGE
13th
STAGE
14th
STAGE
15th
STAGE
16th
STAGE
INPUT DATA
CRC
OUTPUT
Figure 17. DS2408 AS SLAVE INTERFACE FOR MICROCONTROLLER
VCC
DS80C520
P1.0
3
P1.1
4
P1.2
5
P1.3
6
P1.4
7
P1.5
8
P1.6
9
P1.7
10
RST
12
P3.7/ RD
22
P3.6/ WR
21
P3.5/T1
20
P3.4/T0
19
P3.3/ INT1
18
P3.2/ INT0
17
P3.1/TXD0
16
P3.0/RXD0
15
EA
42
XTAL2
23
XTAL1
24
RTCX2
27
RTCX1
28
P2.6/AD14
36
P2.5/AD13
35
P2.4/AD12
34
P2.3/AD11
33
P2.2/AD10
32
P2.7/AD15
37
P2.1/AD9
31
P2.0/AD8
30
PSEN
38
ALE
39
P0.7/AD7
43
P0.6/AD6
44
P0.5/AD5
45
P0.4/AD4
46
P0.3/AD3
47
P0.2/AD2
48
P0.1/AD1
49
P0.0/AD0
50
47U
DS2408
P0
2
P1
14
P2
13
P3
12
P4
11
P5
9
P6
8
P7
7
10
GND
5
VCC
3
IO
4
PULLUP PROVIDED BY CPU
8051 Equiv CPU
GND
VCC
1W
RSTZ
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