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參數(shù)資料
| 型號： | DS2404-001 |
| 英文描述： | EconoRAM Time Chip |
| 中文描述： | EconoRAM時鐘芯片 |
| 文件頁數(shù)： | 24/28頁 |
| 文件大?。?/td> | 663K |
| 代理商： | DS2404-001 |
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DS2404
24 of 28
020998
DUAL PORT OPERATION
The on-chip arbitration logic works on a first-come, first serve principle. Assuming that at one time both
ports are idle, the one port that becomes active prior to the other one is granted access. Activity on the 3-
wire port begins as the voltage level on the
RST
input changes from low to high. The 1-Wire port is
considered active with the first falling edge detected after the presence pulse.
Attempting to communicate with the device through the port that temporarily has no access does not
affect communication through the other port. If communication on the 1-Wire port is initiated while the
3-wire port is active, the device will still respond to the reset pulse, but any subsequently transmitted 1-
Wire command will be ignored. When reading the ROM or memory, for example, the response will
always be 1’s, indicating that access was denied. While the 1-Wire port is active, the 3-wire data line DQ
is in tristate mode. The always present resistor of approximately 60 k
pulls DQ low. The micro
connected to the 3-wire port will fight against this weak pulldown and, depending on its port
haracteristics, possibly dominate the logical value on DQ.
Since writing to the memory of the DS2404 requires multiple steps with short periods where both ports
are inactive, additional measures are required. To avoid one port overwriting actions initiated by the other
port one should do the following:
Allow the microcontroller operating the 3-wire port to monitor the activity on the 1-Wire port. This could
be done by means of a retriggerable one-shot, for example. The microcontroller should wait for a break of
several milliseconds on the 1-Wire port before attempting communication through the 3-wire port.
In addition, data should be organized as data packets with a length byte at the beginning and a CRC check
at the end. Whenever one side has finished communication with the DS2404 it should write a token such
as a “null-packet” into the scratchpad. A null-packet consists of three bytes that represent a zero length
followed by a valid 16-bit CRC. As one port tries to communicate with the device, the first memory
function command should be a Read Scratchpad. Communication should only proceed if the null-packet
is found. Otherwise communication through the other port is not yet finished and one is likely to interfere
if one does not immediately release the port for the communication on the other port to resume. For
details on recommended data structures please refer to chapters 7 or 10 of the “Book of DS19xx iButton
Standards”.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS2404B | EconoRAM Time Chip |
| DS2404S | EconoRAM Time Chip |
| DS2405 | Addressable Switch |
| DS2405P | Addressable Switch |
| DS2405T | Addressable Switch |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS2404-001+ | 制造商:Maxim Integrated Products 功能描述:REAL TIME CLOCK SERL 512BYTE 16PDIP - Rail/Tube |
| DS2404B | 功能描述:實時時鐘 RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| DS2404B/T&R | 制造商:Maxim Integrated Products 功能描述:ECONORAM/TIME, SSOP16-TRL (GENERIC) - Tape and Reel |
| DS2404B+ | 制造商:Maxim Integrated Products 功能描述:REAL TIME CLOCK SERL 512BYTE 16SSOP - Rail/Tube |
| DS2404B+T&R | 制造商:Maxim Integrated Products 功能描述:REAL TIME CLOCK SERL 512BYTE 16SSOP - Tape and Reel |
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