參數(shù)資料
型號(hào)： DS229SN
廠商： DALLAS SEMICONDUCTOR
元件分類： Line Driver or Receiver
英文描述： LINE TRANSCEIVER, PDSO20
封裝： SOIC-20
文件頁(yè)數(shù)： 36/47頁(yè)
文件大?。?/td> 413K
代理商： DS229SN
MAX1464
Low-Power, Low-Noise Multichannel
Sensor Signal Processor
41
Maxim Integrated
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register 00h ADC_Control
X
SE[3]
SE[2]
SE[1]
SE[0]
X
CNVT1
CNVT2
CNVTT
Register 01h ADC_Data_1 (for Channel Input 1, Uncompensated, and Read-Only Register)
MSB
LSB
Register 02h ADC_Config_1A (for Channel 1)
PGA1[4] PGA1[3] PGA1[2] PGA1[1] PGA1[0] CLK1[2] CLK1[1] CLK1[0]
X
RES1[2] RES1[1] RES1[0]
CO1[3]
CO1[2]
CO1[1] CO1[0]
Register 03h ADC_Config_1B (for Channel 1)
X
BIAS1[2] BIAS1[1] BIAS1[0]
X
REF1[1] REF1[0]
Register 04h ADC_Data_2 (for Channel Input 1, Uncompensated, and Read-Only Register)
MSB
LSB
Register 05h ADC_Config_2A (for Channel 2A)
PGA2[4] PGA2[3] PGA2[2] PGA2[1] PGA2[0] CLK2[2] CLK2[1] CLK2[0]
X
RES2[2] RES2[1] RES2[0] CO2[3]
CO2[2]
CO2[1]
CO2[0]
Register 06h ADC_Config_2B (for Channel 2B)
X
BIAS2[2] BIAS2[1] BIAS2[0]
X
REF2[1] REF2[0]
Register 07h ADC Data_T (for Internal Temperature Input, Uncompensated, and Read-Only Register)
MSB
LSB
Register 08h ADC_Config_TA (for Internal Temperature Input TA)
PGAT[4] PGAT[3] PGAT[2] PGAT[1] PGAT[0] CLKT[2] CLKT[1] CLKT[0]
X
REST[2] REST[1] REST[0] COT[3]
COT[2]
COT[1]
COT[0]
Register 09h ADC_Config_TB (for Internal Temperature Input TB)
X
BIAST[2] BIAST[1] BIAST[0]
X
Register 10h DOP1 Data (for DAC/PWM 1)
MSB
LSB
Register 11h DOP1 Control (for DAC/PWM 1)
X
ENPWM1
X
ENDAC1
Register 12h DOP1 Configuration (for DAC/PWM 1)
X
SELPWM1
X
SELDAC1
X
SELREF1
Register 13h DOP2 Data (for DAC/PWM 2)
MSB
LSB
Register 14h DOP2 Control (for DAC/PWM 2)
X
ENPWM2
X
ENDAC2
Register 15h DOP2 Configuration (for DAC/PWM 2)
X
SELPWM2
X
SELDAC2
X
SELREF2
Register 20h Timer Control
TMDN
TMEN
X
ENAHALT
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register 21h Timer Configuration
PS[3]
PS[2]
PS[1]
PS[0]
TO[11]
TO[10]
TO[9]
TO[8]
TO[7]
TO[6]
TO[5]
TO[4]
TO[3]
TO[2]
TO[1]
Register 30h OP AMP Configuration
X
BUF1_LG BUF1_SM
Register 31h Power-On Control
X
PWRA2D
X
PWRDAC2 PWRDAC1
X
PWROP2 PWROP1
Register 32h Oscillator Control
X
OSC[4]
OSC[3]
OSC[2]
OSC[1]
OSC[0]
X
ENCKOUT
Register 40h GPIO1 Control
X
OUT1
EN1
IN1
CLR1
INV1
EDGE1
Register 41h GPIO2 Control
X
OUT2
EN2
IN2
CLR2
INV2
EDGE2
Table 37. Module Registers Summary
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