參數(shù)資料
型號： DS21Q58L+
廠商： Maxim Integrated Products
文件頁數(shù)： 4/74頁
文件大?。?/td> 0K
描述： IC TXRX E1 QUAD 3.3V 100LQFP
產(chǎn)品培訓模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 90
功能： 收發(fā)器
接口： E1
電路數(shù)： 4
電源電壓： 3.14 V ~ 3.47 V
電流 - 電源： 230mA
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 100-LQFP
供應商設備封裝： 100-LQFP（14x14）
包裝： 托盤
包括： AIS 警報檢測器和發(fā)生器，回送功能，PRBS 發(fā)生器 / 檢測器，遠程檢測器和發(fā)生器
產(chǎn)品目錄頁面： 1429 (CN2011-ZH PDF)
DS21Q58 E1 Quad Transceiver
12 of 74
4.1 Pin Function Descriptions
Table 4-3. System (Backplane) Interface Pins
NAME
TYPE
FUNCTION
TCLK
I
Transmit Clock. TCLK is a 2.048MHz primary clock that is used to clock data through the transmit
formatter.
TSER
I
Transmit Serial Data. Transmit NRZ serial data. TSER is sampled on the falling edge of TCLK when
IBO is disabled. It is sampled on the falling edge of SYSCLK when the IBO function is enabled.
TSYNC
I/O
Transmit Sync. As an input, a pulse at this pin establishes either frame or multiframe boundaries for the
transmitter. As an output, it can be programmed to output either a frame or multiframe pulse.
RSER
O
Receive Serial Data. RSER is the received NRZ serial data. RSER is updated on the rising edges of
RCLK when the receive elastic store is disabled. It is updated on the rising edges of SYSCLK when the
receive elastic store is enabled.
RSYNC
I/O
Receive Sync. An extracted pulse one RCLK wide is output at this pin that identifies either frame or
CAS/CRC4 multiframe boundaries. If the receive elastic store is enabled, this pin can be enabled to be
an input at which a frame-boundary pulse synchronous with SYSCLK is applied.
SYSCLK
I
System Clock. SYSCLK is a 2.048MHz clock used to clock data out of the receive elastic store. When
the IBO is enabled SYSCLK can be a 4.096MHz, 8.192MHz, or 16.384MHz clock.
OUTA
O
User-Selectable Output A. OUTA is a multifunction pin the host can program to output various alarms,
clocks, or data, or be used to control external circuitry.
OUTB
O
User-Selectable Output B. OUTB is a multifunction pin the host can program to output various alarms,
clocks, or data, or be used to control external circuitry.
Table 4-4. Alternate Jitter Attenuator
NAME
TYPE
FUNCTION
AJACKI
I
Alternate Jitter Attenuator Clock Input. AJACKI is clock input to the alternate jitter attenuator.
AJACKO
O
Alternate Jitter Attenuator Clock Output. AJACKO is clock output of the alternate jitter attenuator.
Table 4-5. Clock Synthesizer
NAME
TYPE
FUNCTION
4/8/16MCK
O
4.096MHz/8.192MHz/16.384MHz Clock Output. 4/8/16MCK is a 4.096MHz, 8.192MHz, or 16.384MHz
clock output that is referenced to one of the four recovered line clocks (RCLKs) or to an external
2.048MHz reference.
REFCLK
I/O
Reference Clock. REFCLK can be configured as an output to source a 2.048MHz reference clock or as
an input to supply a 2.048MHz reference clock from an external source to the clock synthesizer.
Table 4-6. Parallel Port Control Pins
NAME
TYPE
FUNCTION
INT
O
Interrupt.
INT flags the host controller during conditions and change of conditions defined in status
registers 1 and 2 and the HDLC status register. It is an active-low, open-drain output.
BTS0
I
Bus Type Select Bit 0. BTS0 is used with BTS1 to select between muxed, nonmuxed, serial bus
operation, and output high-Z mode.
BTS1
I
Bus Type Select Bit 1. BTS1 is used with BTS0 to select between muxed, nonmuxed, serial bus
operation, and output high-Z mode.
TS0
I
Transceiver Select Bit 0. TS0 is used with TS1 to select one of four transceivers.
TS1
I
Transceiver Select Bit 1. TS1 is used with TS0 to select one of four transceivers.
PBTS
I
Parallel Bus Type Select. PBTS is used to select between Motorola and Intel parallel bus types.
AD0 to
AD7/SDO
I/O
Data Bus or Address/Data Bus [D0 to D6], Data Bus or Address/Data Bus [D7]/Serial Port Output.
In nonmultiplexed bus operation (MUX = 0), these pins serve as the data bus. In multiplexed bus
operation (MUX = 1), they serve as an 8-bit multiplexed address/data bus.
A0 to A4
I
Address Bus. In nonmultiplexed bus operation, these pins serve as the address bus. In multiplexed bus
operation, these pins are not used and should be wired low.
RD (DS)/SCLK
I
Read Input—Data Strobe/Serial Port Clock.
RD and DS are active-low signals. DS is active high when
in multiplexed mode (Section 26).
CS
I
Chip Select.
CS must be low to read or write to the device. It is an active-low signal.
ALE (AS)/A5
I
Address Latch Enable (Address Strobe) or A6. In nonmultiplexed bus operation, this pin serves as the
upper address bit. In multiplexed bus operation, it demultiplexes the bus on a positive-going edge.
WR (R/W)/SDI
I
Write Input (Read/Write)/Serial Port Data Input, Active Low
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