參數(shù)資料
型號： DS21Q48
英文描述： 5V E1/T1/J1 Line Interface
中文描述： 5V、E1/T1/J1線路接口
文件頁數(shù)： 34/75頁
文件大?。?/td> 544K
代理商： DS21Q48
DS2148/Q48
34 of 76
INTERNAL RX TERMINATION SELECT
Table 6-5
RT1
(CCR5.1)
(CCR5.0)
0
0
1
1
CCR6 (05H): COMMON CONTROL REGISTER 6
(MSB)
LLB
RLB
ARLBE
SYMBOL
POSITION
RT0
INTERNAL RECEIVE
TERMINATION CONFIGURATION
Internal receive-side termination disabled
Internal receive-side 120 enabled
Internal receive-side 100
enabled
Internal receive-side 75 enabled
0
1
0
1
(LSB)
ECRS0
ALB
RJAB
ECRS2
ECRS1
DESCRIPTION
Local Loopback.
In Local Loopback (LLB), transmit data will
be looped back to the receive path passing through the jitter
attenuator if it is enabled. Data in the transmit path will act as
normal. See Figure 3-1 (DS2148 BLOCK DIAGRAM
Figure
3-1 and section 8-2.2 for details.
0 = loopback disabled
1 = loopback enabled
Remote Loopback.
In Remote Loopback (RLB), data output
from the clock/data recovery circuitry will be looped back to the
transmit path passing through the jitter attenuator if it is
enabled. Data in the receive path will act as normal while data
presented at TPOS and TNEG will be ignored. See Figure 3-1
(DS2148 BLOCK DIAGRAM
Figure 3-1
and section 8-2.1 for
details.
0 = loopback disabled
1 = loopback enabled
Automatic Remote Loopback Enable and Reset.
When this
bit is set high, the device will automatically go into remote
loopback when it detects loop-up code programmed into the
receive loop-up code definition registers (RUPCD1 and
RUPCD2) for a minimum of 5 seconds and it will also set the
RIR2.1 status bit. Once in a RLB state, it will remain in this
state until it has detected the loop code programmed into the
receive loop-down code definition registers (RDNCD1 and
RDNCD2) for a minimum of 5 seconds at which point it will
force the device out of RLB and clear RIR2.1. Toggling this bit
from a 1 to a 0 can reset the automatic RLB circuitry. The
action of the automatic remote loopback circuitry is logically
OR’ed with the RLB (CCR6.6) control bit (i.e., either one can
cause a RLB to occur).
Analog Loopback.
In analog loopback (ALB), signals at TTIP
and TRING will be internally connected to RTIP and RRING.
The incoming signals, from the line, at RTIP and RRING will
be ignored. The signals at TTIP and TRING will be transmitted
as normal. See Figure 3-1 (DS2148 BLOCK DIAGRAM
LLB
CCR6.7
RLB
CCR6.6
ARLBE
CCR6.5
ALB
CCR6.4
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相關代理商/技術參數(shù)
參數(shù)描述
DS21Q48A3N 功能描述:網(wǎng)絡控制器與處理器 IC 5V Quad E1/T1/J1 Line Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21Q48B 功能描述:網(wǎng)絡控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21Q48C 功能描述:網(wǎng)絡控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21Q48N 功能描述:網(wǎng)絡控制器與處理器 IC 5V Quad E1/T1/J1 Line Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21Q48NB 功能描述:網(wǎng)絡控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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