參數(shù)資料
型號(hào): DS21Q48
英文描述: 5V E1/T1/J1 Line Interface
中文描述: 5V、E1/T1/J1線路接口
文件頁(yè)數(shù): 17/75頁(yè)
文件大?。?/td> 544K
代理商: DS21Q48
DS2148/Q48
17 of 75
PIN DESCRIPTIONS IN HARDWARE MODE
(Sorted by Pin Name, DS2148T Pin
Numbering) Table 4-4b
ACRONYM
PIN
I/O
DESCRIPTION
BIS0/
BIS1
33
BIS0 = 1 and BIS1 = 1 selects hardware mode.
BPCLK
31
O
Back Plane Clock.
16.384 MHz output.
CES
12
I
Receive & Transmit Clock Edge Select.
Selects which RCLK
edge to update RPOS and RNEG and which TCLK edge to sample
TPOS and TNEG.
0 = update RNEG/RPOS on rising edge of RCLK; sample
TPOS/TNEG on falling edge of TCLK
1 = update RNEG/RPOS on falling edge of RCLK; sample
TPOS/TNEG on rising edge of TCLK
DJA
8
I
Disable Jitter Attenuator.
0 = jitter attenuator enabled
1 = jitter attenuator disabled
EGL
1
I
Receive Equalizer Gain Limit.
This pin controls the sensitivity of
the receive equalizer.
EGL E1 (ETS = 0)
0 = -12dB (short haul)
1 = -43dB (long haul)
EGL T1 (ETS = 1)
0 = -36dB (long haul)
1 = -30dB (limited long haul)
ETS
2
I
E1/T1 Select.
0 = E1
1 = T1
HBE
11
I
Receive & Transmit HDB3/B8ZS Enable.
0 = enable HDB3 (E1)/B8ZS (T1)
1 = disable HDB3 (E1)/B8ZS (T1)
HRST*
29
I
Hardware Reset.
Bringing HRST* low will reset the DS2148.
JAMUX
9
I
Jitter Attenuator MUX.
Controls the source for JACLK. See
Figure 3-1 and Table 4-10.
E1 (ETS = 0) JAMUX
MCLK = 2.048 MHz 0
T1 (ETS = 1)
MCLK = 2.048 MHz 1
MCLK = 1.544 MHz 0
JAS
10
I
Jitter Attenuator Select.
0 = place the jitter attenuator on the receive side
1 = place the jitter attenuator on the transmit side
L0/L1/L2
7/
6/
5
and Table 9-2.
LOOP0/
LOOP1
17
the active loopback mode (if any). See Table 4-5.
32/
I
Bus Interface Select Bits 0 & 1.
Used to select bus interface option.
I
Transmit LIU Waveshape Select Bits 0 & 1 [H/W Mode].
These
inputs determine the waveshape of the transmitter. See Table 9-1
16/
I
Loopback Select Bits 0 & 1 [H/W Mode].
These inputs determine
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