參數(shù)資料
型號: DS21Q44T
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PQFP128
封裝: TQFP-128
文件頁數(shù): 12/105頁
文件大?。?/td> 702K
代理商: DS21Q44T
DS21Q44
14 of 105
3. DS21Q44 PIN FUNCTION DESCRIPTION
TRANSMIT SIDE PINS
Signal Name:
TCLK
Signal Description:
Transmit Clock
Signal Type:
Input
A 2.048 MHz primary clock. Used to clock data through the transmit side formatter.
Signal Name:
TSER
Signal Description:
Transmit Serial Data
Signal Type:
Input
Transmit NRZ serial data. Sampled on the falling edge of TCLK when the transmit side elastic store is
disabled. Sampled on the falling edge of TSYSCLK when the transmit side elastic store is enabled.
Signal Name:
TCHCLK
Signal Description:
Transmit Channel Clock
Signal Type:
Output
A 256-kHz clock which pulses high during the LSB of each channel. Synchronous with TCLK when the
transmit side elastic store is disabled. Synchronous with TSYSCLK when the transmit side elastic store
is enabled. Useful for parallel to serial conversion of channel data. This function is available when FMS
= 1 (DS21Q43 emulation).
Signal Name:
TCHBLK
Signal Description:
Transmit Channel Block
Signal Type:
Output
A user programmable output that can be forced high or low during any of the 32 E1 channels.
Synchronous with TCLK when the transmit side elastic store is disabled. Synchronous with TSYSCLK
when the transmit side elastic store is enabled. Useful for blocking clocks to a serial UART or LAPD
controller in applications where not all E1 channels are used such as Fractional E1, 384 kbps (H0),
768 kbps, 1920 bps (H12) or ISDN–PRI . Also useful for locating individual channels in drop–and–insert
applications, for external per–channel loopback, and for per–channel conditioning. See Section 12 for
details.
相關(guān)PDF資料
PDF描述
DS21Q44TN DATACOM, FRAMER, PQFP128
DS21Q48N DATACOM, PCM TRANSCEIVER, PBGA144
DS21Q48 DATACOM, PCM TRANSCEIVER, PBGA144
DS21Q552 DATACOM, PCM TRANSCEIVER, PBGA256
DS2250-32-16 8-BIT, 16 MHz, MICROCONTROLLER, SMA40
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