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參數(shù)資料
| 型號： | DS21Q43ATN |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 34/60頁 |
| 文件大?。?/td> | 748K |
| 代理商： | DS21Q43ATN |
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DS21Q43A
34 of 60
6.3 Internal Register Scheme Based on CRC4 Multiframe
On the receive side, there is a set of eight registers (RSiAF, RSiNAF, RRA, RSa4 to RSa8) that report the
SI and Sa bits as they are received. These registers are updated with the setting of the Receive CRC4
Multiframe bit in Status Register 2 (SR2.1). The host can use the SR2.1 bit to know when to read these
registers. The user has 2 ms to retrieve the data before it is lost. The MSB of each register is the first
received. Please see the register descriptions below and the Transmit Data Flow diagram in Section 11 for
more details.
On the transmit side, there is also a set of eight registers (TSiAF, TSiNAF, TRA, TSa4 to TSa8) that via
the Transmit Sa Bit Control Register (TSaCR), can be programmed to insert both Si and Sa data. Data is
sampled from these registers with the setting of the Transmit multiframe bit in Status Register 2 (SR2.5).
The host can use the SR2.5 bit to know when to update these registers. It has 2 ms to update the data or
else the old data will be retransmitted. The MSB of each register is the first bit transmitted. Please see the
register descriptions below and the Transmit Data Flow diagram in Section 11 for more details.
REGISTER
NAME
RSiAF
RSiNAF
RRA
RSa4
RSa5
RSa6
RSa7
RSa8
TSiAF
TSiNAF
TTA
TSa4
TSa5
TSa6
TSa7
TSa8
ADDRESS
(HEX)
58
59
5A
5B
5C
5D
5E
5F
50
51
52
53
54
55
56
57
FUNCTION
The eight Si bits in the align frame.
The eight Si bits in the non-align frame.
The eight reportings of the receive remote alarm (RA).
The eight Sa4 reported in each CRC4 multiframe.
The eight Sa5 reported in each CRC4 multiframe.
The eight Sa6 reported in each CRC4 multiframe.
The eight Sa7 reported in each CRC4 multiframe.
The eight Sa8 reported in each CRC4 multiframe.
The eight Si bits to be inserted into the align frame.
The eight Si bits to be inserted into the non-align frame.
The eight settings of receive remote alarm (RA).
The eight Sa4 settings in each CRC4 multiframe.
The eight Sa5 settings in each CRC4 multiframe.
The eight Sa6 settings in each CRC4 multiframe.
The eight Sa7 settings in each CRC4 multiframe.
The eight Sa8 settings in each CRC4 multiframe.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS21Q44 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| DS21Q44T | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| DS21Q44TN | MICROSWITCH, SPDT, SIM ROLLER LEVER; Current, contact AC:5A; Force, operating:91.75gf; Travel, pre:16.0mm; Centres, fixing LxW:22.2mm; Temp, op. max:120(degree C); Temp, op. min:-40(degree C); Length / Height, external:9.25mm; Width, RoHS Compliant: Yes |
| DS2251T-128-16 | CONNECTOR ACCESSORY |
| DS2251T-32-16 | 128k Soft Microcontroller Module |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS21Q43-ATN | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad E1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21Q44 | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:Enhanced QUAD E1 FRAMER |
| DS21Q44T | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Enhanced Quad E1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21Q44T+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Enhanced Quad E1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21Q44TN | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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