參數(shù)資料
型號： DS21FT44+
廠商： Maxim Integrated Products
文件頁數(shù)： 36/117頁
文件大小： 0K
描述： IC FRAMER 4X4 16CH 300-BGA
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 40
控制器類型： E1 調(diào)幀器
接口： 并行/串行
電源電壓： 2.97 V ~ 3.63 V
電流 - 電源： 225mA
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 300-BBGA
供應(yīng)商設(shè)備封裝： 300-PBGA（27x27）
包裝： 管件
DS21FT44/DS21FF44
25 of 117
Signal Name:
RD* (DS*)
Signal Description:
Read Input (Data Strobe)
Signal Type:
Input
RD* and DS* are active-low signals. Note: DS is active high when MUX = 1. See bus timing diagrams in
Section 23.
Signal Name:
FS0 and FS1
Signal Description:
Framer Selects
Signal Type:
Input
Selects which of the four framers to be accessed.
Signal Name:
CS*
Signal Description:
Chip Select
Signal Type:
Input
Must be low to read or write to the device. CS* is an active low signal.
Signal Name:
WR* (R/W*)
Signal Description:
Write Input (Read/Write)
Signal Type:
Input
WR* is an active-low signal.
TEST ACCESS PORT PINS
Signal Name:
Test
Signal Description:
3–State Control
Signal Type:
Input
Set high to tri-state all output and I/O pins (including the parallel control port). Set low for normal
operation. Useful in board level testing.
Signal Name:
JTRST*
Signal Description:
IEEE 1149.1 Test Reset
Signal Type:
Input
This signal is used to asynchronously reset the test access port controller. At power-up, JTRST* must be
set low and then high. This action sets the device into the boundary scan bypass mode allowing normal
device operation. If boundary scan is not used, this pin should be held low. This function is available
when FMS = 0. FMS is connected to ground for the DS21FF44/DS21FT44.
Signal Name:
JTMS
Signal Description:
IEEE 1149.1 Test Mode Select
Signal Type:
Input
This pin is sampled on the rising edge of JTCLK and is used to place the test port into the various defined
IEEE 1149.1 states. If not used, this pin should be pulled high. This function is available when FMS = 0.
FMS is connected to ground for the DS21FF44/DS21FT44.
Signal Name:
JTCLK
Signal Description:
IEEE 1149.1 Test Clock Signal
Signal Type:
Input
This signal is used to shift data into JTDI on the rising edge and out of JTDO on the falling edge. If not
used, this pin should be connected to VSS. This function is available when FMS = 0.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS21FT44+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4X3 E1 Framer E1 Framer E1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21FT44N 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4x4 16/4x3 12 Chnl E1/E1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21FT44N+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4x4 16/4x3 12 Chnl E1/E1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21Q348 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21Q348B 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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