參數(shù)資料
型號: DS21FF42
廠商: Maxim Integrated Products
文件頁數(shù): 46/114頁
文件大?。?/td> 0K
描述: IC FRAMER T1 4X4 16CH 300-BGA
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 40
控制器類型: T1 調(diào)幀器
接口: 并行/串行
電源電壓: 2.97 V ~ 3.63 V
電流 - 電源: 300mA
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 300-BBGA
供應(yīng)商設(shè)備封裝: 300-PBGA(27x27)
包裝: 管件
DS21FT42/DS21FF42
37 of 114
SYMBOL
POSITION
NAME AND DESCRIPTION
RZSE
CCR2.0
Receive FDL Zero Destuffer Enable. Set this bit to zero if
using the internal HDLC/BOC controller instead of the
legacy support for the FDL. See Section 19 for details.
0 = zero destuffer disabled
1 = zero destuffer enabled
CCR3: COMMON CONTROL REGISTER 3 (Address=30 Hex)
(MSB)
(LSB)
RESMDM
TCLKSRC
RLOSF
RSMS
PDE
ECUS
TLOOP
TESMDM
SYMBOL
POSITION
NAME AND DESCRIPTION
RESMDM
CCR3.7
Receive Elastic Store Minimum Delay Mode. See Section
17 for details.
0 = elastic stores operate at full two frame depth
1 = elastic stores operate at 32–bit depth
TCLKSRC
CCR3.6
Transmit Clock Source Select. This function allows the
user to internally select RCLK as the clock source for the
transmit side formatter.
0 = Transmit side formatter clocked with signal applied at
TCLK pin. LOTC Mux function is operational (TCR1.7)
1 = Transmit side formatter clocked with RCLK.
RLOSF
CCR3.5
Function of the RLOS/LOTC Output. Active only when
FMS = 1 (DS21Q41 emulation).
0 = Receive Loss of Sync (RLOS)
1 = Loss of Transmit Clock (LOTC)
FMS is tied to ground for the DS21FF42/DS21FT42.
RSMS
CCR3.4
RSYNC Multiframe Skip Control. Useful in framing
format conversions from D4 to ESF. This function is not
available when the receive side elastic store is enabled.
0 = RSYNC will output a pulse at every multiframe
1 = RSYNC will output a pulse at every other multiframe
note: for this bit to have any affect, the RSYNC must be set
to output multiframe pulses (RCR2.4=1 and RCR2.3=0).
PDE
CCR3.3
Pulse Density Enforcer Enable.
0 = disable transmit pulse density enforcer
1 = enable transmit pulse density enforcer
ECUS
CCR3.2
Error Counter Update Select. See Section 12 for details.
0 = update error counters once a second
1 = update error counters every 42 ms (333 frames)
TLOOP
CCR3.1
Transmit Loop Code Enable. See Section 20 for details.
0 = transmit data normally
1 = replace normal transmitted data with repeating code as
defined in TCD register
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