參數資料
型號: DS21FF42
廠商: Maxim Integrated Products
文件頁數: 33/114頁
文件大小: 0K
描述: IC FRAMER T1 4X4 16CH 300-BGA
產品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 40
控制器類型: T1 調幀器
接口: 并行/串行
電源電壓: 2.97 V ~ 3.63 V
電流 - 電源: 300mA
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 300-BBGA
供應商設備封裝: 300-PBGA(27x27)
包裝: 管件
DS21FT42/DS21FF42
25 of 114
Signal Name:
JTRST*
Signal Description:
IEEE 1149.1 Test Reset
Signal Type:
Input
This signal is used to asynchronously reset the test access port controller. At power up, JTRST* must be
set low and then high. This action will set the device into the DEVICE ID mode allowing normal device
operation. If boundary scan is not used and FMS = 0, this pin should be held low. This function is
available when FMS = 0. When FMS=1, this pin is held LOW internally. This pin is pulled up internally
by a 10K ohm resistor. FMS is tied to ground for the DS21FF42/DS21FT42.
Signal Name:
JTMS
Signal Description:
IEEE 1149.1 Test Mode Select
Signal Type:
Input
This pin is sampled on the rising edge of JTCLK and is used to place the test port into the various defined
IEEE 1149.1 states. This pin is pulled up internally by a 10K ohm resistor. If not used, this pin should
be left unconnected. This function is available when FMS = 0. FMS is tied to ground for the
DS21FF42/DS21FT42.
Signal Name:
JTCLK
Signal Description:
IEEE 1149.1 Test Clock Signal
Signal Type:
Input
This signal is used to shift data into JTDI pin on the rising edge and out of JTDO pin on the falling edge.
If not used, this pin should be connected to VSS. This function is available when FMS = 0. FMS is tied
to ground for the DS21FF42/DS21FT42.
Signal Name:
JTDI
Signal Description:
IEEE 1149.1 Test Data Input
Signal Type:
Input
Test instructions and data are clocked into this pin on the rising edge of JTCLK. This pin is pulled up
internally by a 10K ohm resistor. If not used, this pin should be left unconnected. This function is
available when FMS = 0. FMS is tied to ground for the DS21FF42/DS21FT42.
Signal Name:
JTDO
Signal Description:
IEEE 1149.1 Test Data Output
Signal Type:
Output
Test instructions and data are clocked out of this pin on the falling edge of JTCLK. If not used, this pin
should be left unconnected. This function is available when FMS = 0. FMS is tied to ground for the
DS21FF42/DS21FT42.
SUPPLY PINS
Signal Name:
VDD
Signal Description:
Positive Supply
Signal Type:
Supply
2.97 to 3.63 volts.
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