- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379182 > DS2188 T1/CEPT Jitter Attenuator PDF資料下載
參數(shù)資料
| 型號： | DS2188 |
| 英文描述： | T1/CEPT Jitter Attenuator |
| 中文描述： | T1/CEPT抖動抑制器 |
| 文件頁數(shù)： | 1/11頁 |
| 文件大小： | 149K |
| 代理商： | DS2188 |
1 of 11
092299
FEATURES
§
Attenuates clock and data jitter present in T1
or CEPT lines
§
Meets the jitter attenuation templates
outlined in TR62411, TR-TSY-000170,
G.735, and G.742
§
Only one external component required; either
a 6.176 MHz (T1) or 8.192 MHz (CEPT)
crystal
§
Selectable buffer size of 128 or 32 bits
§
Jitter attenuation is easily disabled
§
Single +5V supply; low-power CMOS
technology
§
Available in 16-pin DIP and 16-pin SOIC
(DS2188S)
§
Companion to the DS2186 Transmit Line
and DS2187 Receive Line Interface
PIN ASSIGNMENT
DESCRIPTION
The DS2188 T1/CEPT Jitter Attenuator Chip contains a 128 X 2-bit buffer which, in conjunction with an
external 4X crystal, is used to attenuate the incoming jitter present in clock and data. The device meets all
of the latest applicable specifications including those outlined in TR 62411 (Accunet* T1.5 Service
Description and Interface Specifications, December 1990), TR-TSY-000170 (Digital Cross-Connect
System Requirements and Objectives, November 1985), and the CCITT Recommendations G.735 and
G.742. The DS2188 is compatible with the DS2180A T1/ISDN Primary Rate Transceiver and DS2181A
CEPT Transceiver and is the companion to the DS2187 T1/CEPT Receive Line Interface and DS2186
T1/CEPT Transmit Line Interface. It can also be used in conjunction with the DS2190 T1 Network
Interface Unit.
OVERVIEW
The RCLK input is fed to a 128 x 2-bit FIFO where it drives the write pointer for the positive (RPOS) and
negative (RNEG) data. The read pointer of the FIFO and RRCLK is generated by dividing the frequency
of the crystal connected to XTAL1 and XTAL2 by four. The frequency of the crystal is adjusted by a
DPLL to the long-term average frequency of RCLK. As long as the jitter present at RCLK is less than
120 unit intervals peak-to-peak (UIpp), then the FIFO buffer will be able to absorb the incoming jitter and
it will be attenuated in accordance with TR 62411 (December 1990). In this situation, the BL (Buffer
Limit) pin will remain low. Figures 1 and 2 illustrate the DS2188 Jitter Attenuator performance.
DS2188
T1/CEPT Jitter Attenuator
www.dalsemi.com
DJA
RPOS
RNEG
RCLK
BDS
TEST
XTAL OUT
VSS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
RRPOS
RRNEG
RRCLK
RST
BL
XTAL2
XTAL1
16-Pin DIP/SOIC
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS2196 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| DS2196L | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| DS2196LN | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| DS21Q43AT | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| DS21Q43ATN | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS2188+ | 功能描述:通信集成電路 - 若干 RoHS:否 制造商:Maxim Integrated 類型:Transport Devices 封裝 / 箱體:TECSBGA-256 數(shù)據(jù)速率:100 Mbps 電源電壓-最大:1.89 V, 3.465 V 電源電壓-最小:1.71 V, 3.135 V 電源電流:50 mA, 225 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Tube |
| DS2188N | 功能描述:通信集成電路 - 若干 RoHS:否 制造商:Maxim Integrated 類型:Transport Devices 封裝 / 箱體:TECSBGA-256 數(shù)據(jù)速率:100 Mbps 電源電壓-最大:1.89 V, 3.465 V 電源電壓-最小:1.71 V, 3.135 V 電源電流:50 mA, 225 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Tube |
| DS2188S | 功能描述:通信集成電路 - 若干 RoHS:否 制造商:Maxim Integrated 類型:Transport Devices 封裝 / 箱體:TECSBGA-256 數(shù)據(jù)速率:100 Mbps 電源電壓-最大:1.89 V, 3.465 V 電源電壓-最小:1.71 V, 3.135 V 電源電流:50 mA, 225 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Tube |
| DS2188S/T&R | 功能描述:通信集成電路 - 若干 RoHS:否 制造商:Maxim Integrated 類型:Transport Devices 封裝 / 箱體:TECSBGA-256 數(shù)據(jù)速率:100 Mbps 電源電壓-最大:1.89 V, 3.465 V 電源電壓-最小:1.71 V, 3.135 V 電源電流:50 mA, 225 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Tube |
| DS2188S+ | 功能描述:通信集成電路 - 若干 RoHS:否 制造商:Maxim Integrated 類型:Transport Devices 封裝 / 箱體:TECSBGA-256 數(shù)據(jù)速率:100 Mbps 電源電壓-最大:1.89 V, 3.465 V 電源電壓-最小:1.71 V, 3.135 V 電源電流:50 mA, 225 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Tube |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。