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參數(shù)資料
| 型號： | DS21554LN |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 62/124頁 |
| 文件大小： | 0K |
| 描述： | IC TXRX E1 1-CHIP 5V 100-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS |
| 產(chǎn)品變化通告： | Product Discontinuation 20/Feb/2012 |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 功能： | 單芯片收發(fā)器 |
| 接口： | E1，HDLC，J1，T1 |
| 電路數(shù)： | 1 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 電流 - 電源： | 75mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-LQFP（14x14） |
| 包裝： | 托盤 |
| 包括： | 遠(yuǎn)程和 AIS 警報檢測器 / 發(fā)生器 |
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DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
42 of 124
CCR6: COMMON CONTROL REGISTER 6 (Address = 1D Hex)
(MSB)
(LSB)
LIUODO
CDIG
LIUSI
—
TCLKSRC
RESR
TESR
SYMBOL
POSITION
NAME AND DESCRIPTION
LIUODO
CCR6.7
Line Interface Open-Drain Option. This control bit determines whether
the TTIP and TRING outputs will be open drain or not. The line driver
outputs can be forced open drain to allow 6Vpeak pulses to be generated
or to allow the creation of a very low power interface.
0 = allow TTIP and TRING to operate normally
1 = force the TTIP and TRING outputs to be open drain
CDIG
CCR6.6
Customer Disconnect Indication Generator. This control bit
determines whether the Line Interface will generate an unframed
...1010... pattern at TTIP and TRING instead of the normal data pattern.
0 = generate normal data at TTIP and TRING as input via TPOSI and
TNEGI
1 = generates a ...1010... pattern at TTIP and TRING
LIUSI
CCR6.5
Line Interface G.703 Synchronization Interface Enable. This control
bit determines whether the line receiver should handle a normal E1 signal
(Section 6 of G.703) or a 2.048MHz synchronization signal (Section 10
of G.703). This control has no affect on the line interface transmitter.
0 = line receiver configured to support a normal E1 signal
1 = line receiver configured to support a synchronization signal
—
CCR6.4
Not Assigned. Should be set to zero when written.
—
CCR6.3
Not Assigned. Should be set to zero when written.
TCLKSRC
CCR6.2
Transmit Clock Source Select. This function allows the user to
internally select RCLK as the clock source for the transmit-side
formatter.
0 = Source of transmit clock determined by CCR2.2 (LOTCMC)
1 = Force transmitter to internally switch to RCLK as source of transmit
clock. Signal at TCLK pin is ignored
RESR
CCR6.1
Receive Elastic Store Reset. Setting this bit from a zero to a one will
force the receive elastic store to a depth of one frame. Receive data is lost
during the reset. Should be toggled after RSYSCLK has been applied and
is stable. Must be cleared and set again for a subsequent reset.
TESR
CCR6.0
Transmit Elastic Store Reset. Setting this bit from a zero to a one will
force the transmit elastic store to a depth of one frame. Transmit data is
lost during the reset. Should be toggled after TSYSCLK has been applied
and is stable. Must be cleared and set again for a subsequent reset.
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|---|---|
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| VE-B6X-IY-B1 | CONVERTER MOD DC/DC 5.2V 50W |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS21554LN+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3/5V E1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2155DK | 功能描述:網(wǎng)絡(luò)開發(fā)工具 RoHS:否 制造商:Rabbit Semiconductor 產(chǎn)品:Development Kits 類型:Ethernet to Wi-Fi Bridges 工具用于評估:RCM6600W 數(shù)據(jù)速率:20 Mbps, 40 Mbps 接口類型:802.11 b/g, Ethernet 工作電源電壓:3.3 V |
| DS2155G | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC T1/E1/J1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2155G/T&R | 制造商:Maxim Integrated Products 功能描述:DS2155 T1/E1/J1 SCT 100P CSBGA T&R - Tape and Reel 制造商:Maxim Integrated Products 功能描述:IC LIU T1/E1/J1 SCT 100P CSBGA 制造商:Maxim Integrated Products 功能描述:Network Controller & Processor ICs T1/E1/J1 Transceiver |
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