3.1.4. JTAG Test Access Port Pins Signal Name: JTRST Signal Description: I" />
參數(shù)資料
型號： DS21554L+
廠商： Maxim Integrated Products
文件頁數(shù)： 40/124頁
文件大?。?/td> 0K
描述： IC TXRX E1 1-CHIP 5V 100-LQFP
產品培訓模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 90
功能： 單芯片收發(fā)器
接口： E1，HDLC，J1，T1
電路數(shù)： 1
電源電壓： 4.75 V ~ 5.25 V
電流 - 電源： 75mA
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 100-LQFP
供應商設備封裝： 100-LQFP（14x14）
包裝： 托盤
包括： 遠程和 AIS 警報檢測器 / 發(fā)生器
產品目錄頁面： 1430 (CN2011-ZH PDF)
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
22 of 124
3.1.4.
JTAG Test Access Port Pins
Signal Name:
JTRST
Signal Description:
IEEE 1149.1 Test Reset
Signal Type:
Input
This signal is used to asynchronously reset the test access port controller. At power up,
JTRST must be
toggled from low to high. This action will set the device into JTAG DEVICE ID mode enabling the test
access port features. This pin has a 10k
W pullup resistor. When FMS = 1, this pin is tied low internally.
Tie
JTRST low if JTAG is not used and the framer is in DS21354/DS21554 mode (FMS low).
Signal Name:
JTMS
Signal Description:
IEEE 1149.1 Test Mode Select
Signal Type:
Input
This pin is sampled on the rising edge of JTCLK and is used to place the test access port into the various
defined IEEE 1149.1 states. This pin has a 10k
W pullup resistor.
Signal Name:
JTCLK
Signal Description:
IEEE 1149.1 Test Clock Signal
Signal Type:
Input
This signal is used to shift data into JTDI on the rising edge and out of JTDO on the falling edge.
Signal Name:
JTDI
Signal Description:
IEEE 1149.1 Test Data Input
Signal Type:
Input
Test instructions and data are clocked into this pin on the rising edge of JTCLK. This pin has a 10k
W
pullup resistor.
Signal Name:
JTDO
Signal Description:
IEEE 1149.1 Test Data Output
Signal Type:
Output
Test instructions and data are clocked out of this pin on the falling edge of JTCLK. If not used, this pin
should be left unconnected.
3.1.5.
Interleave Bus Operation Pins
Signal Name:
CI
Signal Description:
Carry In
Signal Type:
Input
A rising edge on this pin causes RSER and RSIG to come out of high-Z state and TSER and TSIG to start
sampling on the next rising edge of RSYSCLK/TSYSCLK beginning an I/O sequence of 8 or 256 bits of
data. This pin has a 10k
W pullup resistor.
Signal Name:
CO
Signal Description:
Carry Out
Signal Type:
Output
An output that is set high when the last bit of the 8 or 256 IBO output sequence has occurred on RSER
and RSIG.
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相關代理商/技術參數(shù)
參數(shù)描述
DS21554L+ 功能描述:網(wǎng)絡控制器與處理器 IC 3.3/5V E1 Transceiver RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21554LB 功能描述:網(wǎng)絡控制器與處理器 IC 3.3/5V E1 Transceiver RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21554LB+ 功能描述:網(wǎng)絡控制器與處理器 IC 3.3/5V E1 Transceiver RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21554LBN 功能描述:網(wǎng)絡控制器與處理器 IC RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21554LBN+ 功能描述:網(wǎng)絡控制器與處理器 IC 3.3/5V E1 Transceiver RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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