參數(shù)資料
型號: DS2154L
廠商: Maxim Integrated Products
文件頁數(shù): 26/87頁
文件大?。?/td> 0K
描述: IC TXRX E1 1CHIP 5V ENH 100-LQFP
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
產(chǎn)品變化通告: Product Discontinuation 20/Feb/2012
標準包裝: 90
類型: 收發(fā)器
驅(qū)動器/接收器數(shù): 1/1
規(guī)程: E1
電源電壓: 4.75 V ~ 5.25 V
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應商設備封裝: 100-LQFP(14x14)
包裝: 管件
產(chǎn)品目錄頁面: 1429 (CN2011-ZH PDF)
DS2154
32 of 87
RIR: RECEIVE INFORMATION REGISTER (Address = 08 Hex)
(MSB)
(LSB)
TESF
TESE
JALT
RESF
RESE
CRCRC
FASRC
CASRC
SYMBOL
POSITION
NAME AND DESCRIPTION
TESF
RIR.7
Transmit Side Elastic Store Full. Set when the transmit side
elastic store buffer fills and a frame is deleted.
TESE
RIR.6
Transmit Side Elastic Store Empty. Set when the transmit side
elastic store buffer empties and a frame is repeated.
JALT
RIR.5
Jitter Attenuator Limit Trip. Set when the jitter attenuator
FIFO reaches to within 4 bits of its limit; useful for debugging
jitter attenuation operation.
RESF
RIR.4
Receive Side Elastic Store Full. Set when the receive side
elastic store buffer fills and a frame is deleted.
RESE
RIR.3
Receive Side Elastic Store Empty. Set when the receive side
elastic store buffer empties and a frame is repeated.
CRCRC
RIR.2
CRC Resync Criteria Met. Set when 915/1000 code words are
received in error.
FASRC
RIR.1
FAS Resync Criteria Met. Set when 3 consecutive FAS words
are received in error.
CASRC
RIR.0
CAS Resync Criteria Met. Set when 2 consecutive CAS MF
alignment words are received in error.
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