參數(shù)資料
型號: DS2154L
廠商: Maxim Integrated Products
文件頁數(shù): 20/87頁
文件大?。?/td> 0K
描述: IC TXRX E1 1CHIP 5V ENH 100-LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
產(chǎn)品變化通告: Product Discontinuation 20/Feb/2012
標(biāo)準(zhǔn)包裝: 90
類型: 收發(fā)器
驅(qū)動器/接收器數(shù): 1/1
規(guī)程: E1
電源電壓: 4.75 V ~ 5.25 V
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應(yīng)商設(shè)備封裝: 100-LQFP(14x14)
包裝: 管件
產(chǎn)品目錄頁面: 1429 (CN2011-ZH PDF)
DS2154
27 of 87
CCR3: COMMON CONTROL REGISTER 3 (Address = 1B Hex)
(MSB)
(LSB)
TESE
TCBFS
TIRFS
ESR
RSRE
THSE
TBCS
RCLA
SYMBOL
POSITION
NAME AND DESCRIPTION
TESE
CCR3.7
Transmit Side Elastic Store Enable.
0 = elastic store is bypassed
1 = elastic store is enabled
TCBFS
CCR3.6
Transmit Channel Blocking Registers (TCBR) Function
Select.
0 = TCBRs define the operation of the TCHBLK output pin
1 = TCBRs define which signaling bits are to be inserted
TIRFS
CCR3.5
Transmit Idle Registers (TIR) Function Select. See Section 9
for details.
0 = TIRs define in which channels to insert idle code
1 = TIRs define in which channels to insert data from RSER
(i.e., Per-Channel Loopback function)
ESR
CCR3.4
Elastic Stores Reset. Setting this bit from a 1 to a 0 will force
the elastic stores to a known depth. ESR is level triggered.
Should be toggled after RSYSCLK and TSYSCLK have been
applied and are stable. Must be set and cleared again for a
subsequent reset. Do not leave this bit set high.
RSRE
CCR3.3
Receive Side Signaling Re-Insertion Enable. See Section 8.2
for details.
0 = do not reinsert signaling bits into the data stream presented
at the RSER pin
1 = reinsert the signaling bits into data stream presented at the
RSER pin
THSE
CCR3.2
Transmit Side Hardware Signaling Insertion Enable. See
Section 8.2 for details.
0 = do not insert signaling from the TSIG pin into the data
stream presented at the TSER pin
1 = insert signaling from the TSIG pin into the data stream
presented at the TSER pin
TBCS
CCR3.1
Transmit Side Backplane Clock Select.
0 = if TSYSCLK is 1.544MHz
1 = if TSYSCLK is 2.048MHz
RCLA
CCR3.0
Receive Carrier Loss (RCL) Alternate Criteria.
0 = RCL declared upon 255 consecutive 0s (125
s)
1 = RCL declared upon 2048 consecutive 0s (1ms)
相關(guān)PDF資料
PDF描述
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