參數(shù)資料
型號(hào)： DS2148TN
英文描述： 5V E1/T1/J1 Line Interface
中文描述： 5V的E1/T1/J1線(xiàn)路接口
文件頁(yè)數(shù)： 14/75頁(yè)
文件大小： 544K
代理商： DS2148TN
DS2148/Q48
14 of 75
PIN DESCRIPTIONS IN SERIAL PORT MODE
(Sorted by Pin Name, DS2148T
Pin Numbering) Table 4-3b
ACRONYM
PIN
I/O
DESCRIPTION
BIS0/
BIS1
33
See Table 4-1 for details.
BPCLK
31
O
Back Plane Clock.
A 16.384MHz, 8.192MHz, 4.096MHz, or
2.048MHz clock output that is referenced to RCLK selectable via
CCR5.7 and CCR5.6. In hardware mode, defaults to 16.384MHz
output.
CS*
1
I
Chip Select.
Must be low to read or write to the device. CS* is an
active low signal.
HRST*
29
I
Hardware Reset.
Bringing HRST* low will reset the DS2148
setting all control bits to their default state of all zeros.
ICES
8
I
Input Clock Edge Select.
Selects whether the serial port data input
(SDI) is sampled on rising (ICES =0) or falling edge (ICES = 1) of
SCLK.
INT*
23
O
Interrupt [INT*] pin 23.
Flags host controller during conditions
and change of conditions defined in the Status Register. Active low,
open drain output.
MCLK
30
I
Master Clock.
A 2.048MHz (±50ppm) clock source with TTL
levels is applied at this pin. This clock is used internally for both
clock/data recovery and for jitter attenuation. Use of a T1 1.544MHz
clock source is optional.
See Note 1 on clock accuracy at the end of this table.
NA
-
I
Not Assigned.
Should be tied low.
OCES
9
I
Output Clock Edge Select.
Selects whether the serial port data
output (SDO) is valid on the rising (OCES = 1) or falling edge
(OCES = 0) of SCLK.
PBEO
24
O
PRBS Bit Error Output.
The receiver will constantly search for a
2
15
-1 or a 2
20
-1 PRBS depending on the ETS bit setting (CCR1.7).
Remains high if out of synchronization with the PRBS pattern.
Goes low when synchronized to the PRBS pattern. Any errors in the
received pattern after synchronization will cause a positive going
pulse (with same period as E1 or T1 clock) synchronous with
RCLK. PRBS bit errors can also be reported to the ECR1 and
ECR2 registers by setting CCR6.2 to a logic 1.
RCLK
40
O
Receive Clock.
Synchronous to MCLK in absence of signal at RTIP and RRING.
RCL/
LOTC
will toggle high during a receive carrier loss (CCR2.7 = 0) or will
toggle high if the TCLK pin has not been toggled for 5 sec 2
sec (CCR2.7 = 1). CCR2.7 defaults to logic 0 when in hardware
mode.
32/
I
Bus Interface Select Bits 0 & 1.
Used to select bus interface option.
Buffered recovered clock from the line.
25
O
Receive Carrier Loss / Loss of Transmit Clock.
An output which
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS2148TN+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 5V E1/T1/J1 Line Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS2148TNB 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS2148TNC 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS2148TN-W 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS2149 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:5V T1/J1 Line Interface Unit
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