參數(shù)資料
型號(hào)： DS2148T
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 10/73頁(yè)
文件大?。?/td> 0K
描述： IC LIU E1/T1/J1 5V 44-TQFP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
產(chǎn)品變化通告： Product Discontinuation 20/Feb/2012
標(biāo)準(zhǔn)包裝： 160
類(lèi)型： 線路接口裝置（LIU）
驅(qū)動(dòng)器/接收器數(shù)： 1/1
規(guī)程： T1/E1/J1
電源電壓： 4.75 V ~ 5.25 V
安裝類(lèi)型： 表面貼裝
封裝/外殼： 44-TQFP
供應(yīng)商設(shè)備封裝： 44-TQFP（10x10）
包裝： 管件
DS2148/DS21Q48
18 of 73
Table 2-7. Pin Description in Hardware Mode (Sorted by Pin Name, DS2148T)
NAME
PIN
I/O
FUNCTION
BIS0/BIS1
32/33
I
Bus Interface Select Bits 0 & 1. Used to select bus interface option. BIS0 = 1
and BIS1 = 1 selects hardware mode.
BPCLK
31
O
Backplane Clock. 16.384MHz output.
CES
12
I
Receive & Transmit Clock Edge Select. Selects which RCLK edge to update
RPOS and RNEG and which TCLK edge to sample TPOS and TNEG.
0 = update RNEG/RPOS on rising edge of RCLK; sample TPOS/TNEG on
falling edge of TCLK
1 = update RNEG/RPOS on falling edge of RCLK; sample TPOS/TNEG on
rising edge of TCLK
DJA
8
I
Disable Jitter Attenuator
0 = jitter attenuator enabled
1 = jitter attenuator disabled
EGL
1
I
Receive Equalizer Gain Limit. This pin controls the sensitivity of the receive
equalizer.
EGL E1 (ETS = 0)
0 = -12dB (short haul)
1 = -43dB (long haul)
EGL
T1 (ETS = 1)
0 = -36dB (long haul)
1 = -30dB (limited long haul)
ETS
2
I
E1/T1 Select.
0 = E1
1 = T1
HBE
11
I
Receive & Transmit HDB3/B8ZS Enable.
0 = enable HDB3 (E1)/B8ZS (T1)
1 = disable HDB3 (E1)/B8ZS (T1)
HRST
29
I
Hardware Reset. Bringing
HRST low will reset the DS2148.
JAMUX
9
I
Jitter Attenuator MUX. Controls the source for JACLK. See Figure 1-1 and
E1 (ETS = 0)
JAMUX
MCLK = 2.048MHz
0
T1 (ETS = 1)
MCLK = 2.048MHz
1
MCLK = 1.544MHz
0
JAS
10
I
Jitter Attenuator Select
0 = place the jitter attenuator on the receive side
1 = place the jitter attenuator on the transmit side
L0/L1/L2
7/6/5
I
Transmit LIU Waveshape Select Bits 0 & 1 [H/W Mode]. These inputs
determine the waveshape of the transmitter. See Table 7-1 and Table 7-2.
LOOP0/
LOOP1
16/17
I
Loopback Select Bits 0 & 1 [H/W Mode]. These inputs determine the active
loopback mode (if any). See Table 2-8.
MCLK
30
I
Master Clock. A 2.048MHz (±50ppm) clock source with TTL levels is applied
at this pin. This clock is used internally for both clock/data recovery and for jitter
attenuation. Use of a T1 1.544MHz clock source is optional. G.703 requires an
accuracy of
±50ppm for both T1 and E1. TR62411 and ANSI specs require an
accuracy of
±32ppm for T1 interfaces.
MM0/MM1
18/19
I
Monitor Mode Select Bits 0 & 1 [H/W Mode]. These inputs determine if the
receive equalizer is in a monitor mode. See Table 2-11.
NA
-
I
Not Assigned. Should be tied low.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS2148T+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 5V E1/T1/J1 Line Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS2148TA2 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 5V E1/T1/J1 Line Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS2148TB 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS2148TC1 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS2148TN 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 5V E1/T1/J1 Line Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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