參數(shù)資料
型號: DS2148G
英文描述: 5V E1/T1/J1 Line Interface
中文描述: 5V的E1/T1/J1線路接口
文件頁數(shù): 46/75頁
文件大?。?/td> 544K
代理商: DS2148G
DS2148/Q48
46 of 75
FUNCTION OF ECRS BITS AND RNEG PIN
Table 8-4
E1 or T1
(CCR1.7)
(CCR6.2)
(CCR6.1)
0
0
0
0
0
0
0
0
1
0
0
1
1
0
X
1
0
X
1
0
X
1
0
X
X
1
X
NOTES:
1) RNEG outputs error data only when in NRZ mode (CCR1.6 = 1).
2) PRBS errors will always be output at PBEO independent of ECR control bits and NRZ mode and will
not be present at RNEG.
8.4.1 Error Counter Update
A transition of the ECUE (CCR1.4) control bit from 0 to 1 will update the ECR registers with the current
values and reset the counters. ECUE must be set back to zero and another 0 to 1 transition must occur for
subsequent reads/resets of the ECR registers. Note that the DS2148 can report errors at RNEG when in
NRZ mode (CCR1.6 = 1) by outputting a pulse for each error occurrence. The counter saturates at 65,535
and will not rollover.
ECR1 (11H): UPPER ERROR COUNT REGISTER 1
ECR2 (12H): LOWER ERROR COUNT REGISTER 2
(MSB)
E15
E14
E13
E12
E11
E7
E6
E5
E4
E3
SYMBOL
POSITION
DESCRIPTION
E15
ECR1.7
MSB of the 16-bit error count
E0
ECR2.0
LSB of the 16-bit error count
8.5
Error Insertion
When IBPV (CCR3.1) is transitioned from a zero to a one, the device waits for the next occurrence of
three consecutive ones to insert a BPV. IBPV must be cleared and set again for another BPV error
insertion. See figure 3-3 for details on the insertion of the BPV into the datastream.
When IBE (CCR3.0) is transitioned from a zero to a one, the device will insert a logic error. IBE must be
cleared and set again for another logic error insertion. See figure 3-3 for details on the insertion of the
logic error into the datastream.
ECRS2
ECRS1
ECRS0
(CCR6.0)
0
1
0
1
0
1
0
1
X
RHBE
(CCR2.3)
X
X
X
X
0
0
1
1
X
FUNCTION OF ECR
COUNTERS/RNEG
1
CVs
BPVs (HDB3 code words not counted)
CVs + EXZs
BPVs + EXZs
BPVs (B8ZS code words not counted)
BPVs + 8 EXZs
BPVs
BPVs + 16 EXZs
PRBS Errors
2
(LSB)
E8
E0
E10
E2
E9
E1
ECR1
ECR2
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