參數(shù)資料
型號： DS2148G
英文描述： 5V E1/T1/J1 Line Interface
中文描述： 5V的E1/T1/J1線路接口
文件頁數(shù)： 30/75頁
文件大?。?/td> 544K
代理商： DS2148G
DS2148/Q48
30 of 75
CCR3 (02H): COMMON CONTROL REGISTER 3
(MSB)
TUA1
ATUA1
TAOZ
SYMBOL
POSITION
(LSB)
IBE
TPRBSE
TLCE
LIRST
IBPV
DESCRIPTION
Transmit Unframed All Ones.
The polarity of this bit is set
such that the device will transmit an all ones pattern on power-
up or device reset. This bit must be set to a one to allow the
device to transmit data. The transmission of this data pattern is
always timed off of the JACLK (See Figure 3-1).
0 = transmit all ones at TTIP and TRING
1 = transmit data normally
Automatic Transmit Unframed All Ones.
Automatically
transmit an unframed all ones pattern at TTIP and TRING
during a receive carrier loss (RCL) condition or a receive all
ones condition.
0 = disabled
1 = enabled
Transmit Alternate Ones and Zeros.
Transmit a …101010…
pattern at TTIP and TRING. The transmission of this data
pattern is always timed off of TCLK (Figure 3-1).
0 = disabled
1 = enabled
Transmit PRBS Enable.
Transmit a 2
15
- 1 (E1) or a 2
20
- 1
(T1) PRBS at TTIP and TRING. See figure 3-3.
0 = disabled
1 = enabled
Transmit Loop Code Enable.
Enables the transmit side to
transmit the loop up code in the Transmit Code Definition
registers (TCD1 and TCD2). See Section 6 and figure 3-3 for
details.
0 = disabled
1 = enabled
Line Interface Reset.
Setting this bit from a zero to a one will
initiate an internal reset that resets the clock recovery state
machine and re-centers the jitter attenuator. Normally this bit is
only toggled on power-up. Must be cleared and set again for a
subsequent reset.
Insert BPV.
A 0 to 1 transition on this bit will cause a single
BiPolar Violation (BPV) to be inserted into the transmit data
stream. Once this bit has been toggled from a 0 to a 1, the
device waits for the next occurrence of three consecutive ones
to insert the BPV. This bit must be cleared and set again for a
subsequent error to be inserted. See figure 3-3.
Insert Bit Error.
A 0 to 1 transition on this bit will cause a
single logic error to be inserted into the transmit data stream.
This bit must be cleared and set again for a subsequent error to
be inserted. See Figure 3-3.
TUA1
CCR3.7
ATUA1
CCR3.6
TAOZ
CCR3.5
TPRBSE
CCR3.4
TLCE
CCR3.3
LIRST
CCR3.2
IBPV
CCR3.1
IBE
CCR3.0
相關(guān)PDF資料
PDF描述
DS2148GN 5V E1/T1/J1 Line Interface
DS2148T 5V E1/T1/J1 Line Interface
DS2148TN 5V E1/T1/J1 Line Interface
DS21Q48 5V E1/T1/J1 Line Interface
DS21Q48N 5V E1/T1/J1 Line Interface
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS2148G+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 5V E1/T1/J1 Line Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS2148GB 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS2148GN 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS2148GN+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 5V E1/T1/J1 Line Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS2148GNB 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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