參數(shù)資料
型號(hào): DS2148
英文描述: 5V E1/T1/J1 Line Interface
中文描述: 5V、E1/T1/J1線路接口
文件頁(yè)數(shù): 31/75頁(yè)
文件大?。?/td> 544K
代理商: DS2148
DS2148/Q48
31 of 75
6.1
The DS2148 will reset itself upon power-up, setting all writeable registers to 00h and clearing the status
and information registers. CCR3.7 (TUA1) = 0 results in the LIU transmitting unframed all ones. After
the power supplies have settled following power-up, initialize all control registers to the desired settings,
then toggle the LIRST bit (CCR3.2). The DS2148 can be reset at anytime to the default settings by
bringing HRST* (pin 29) low (level triggered) or by powering down and powering up again.
CCR4 (03H): COMMON CONTROL REGISTER 4
(MSB)
L2
L1
L0
EGL
SYMBOL
POSITION
DESCRIPTION
L2
CCR4.7
Line Build Out Select Bit 2.
Sets the transmitter build out
(Table 9-1 for E1 and Table 9-2 for T1)
L1
CCR4.6
Line Build Out Select Bit 1.
Sets the transmitter build out
(Table 9-1 for E1 and Table 9-2 for T1)
L0
CCR4.5
Line Build Out Select Bit 0.
Sets the transmitter build out
(Table 9-1 for E1 and Table 9-2 for T1)
EGL
CCR4.4
Receive Equalizer Gain Limit.
This bit controls the sensitivity
of the receive equalizer (Table 6-2)
JAS
CCR4.3
Jitter Attenuator Select.
0 = place the jitter attenuator on the receive side
1 = place the jitter attenuator on the transmit side
JABDS
CCR4.2
Jitter Attenuator Buffer Depth Select.
0 = 128 bits
1 = 32 bits (use for delay sensitive applications)
DJA
CCR4.1
Disable Jitter Attenuator.
0 = jitter attenuator enabled
1 = jitter attenuator disabled
TPD
CCR4.0
Transmit Power-Down.
0 = normal transmitter operation
1 = powers down the transmitter and 3-states the TTIP and
TRING pins
RECEIVE SENSITIVITY SETTINGS
Table 6-2
EGL
(CCR4.4)
(CCR1.7)
0
0 (E1)
1
0 (E1)
1
1 (T1)
0
1 (T1)
Device Power-Up And Reset
(LSB)
TPD
JAS
JABDS
DJA
ETS
RECEIVE SENSITIVITY
-12dB (short haul)
-43dB (long haul)
-30dB (limited long haul)
-36dB (long haul)
相關(guān)PDF資料
PDF描述
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