參數(shù)資料
型號： DS2148
英文描述： 5V E1/T1/J1 Line Interface
中文描述： 5V、E1/T1/J1線路接口
文件頁數(shù)： 18/75頁
文件大?。?/td> 544K
代理商： DS2148
DS2148/Q48
18 of 75
ACRONYM
PIN
I/O
DESCRIPTION
Master Clock.
A 2.048MHz (±50ppm) clock source with TTL
levels is applied at this pin. This clock is used internally for both
clock/data recovery and for jitter attenuation. Use of a T1 1.544MHz
clock source is optional. G.703 requires an accuracy of 50ppm for
both T1 and E1. TR62411 and ANSI specs require an accuracy of
32ppm for T1 interfaces.
Monitor Mode Select Bits 0 & 1 [H/W Mode].
These inputs
determine if the receive equalizer is in a monitor mode.
See Table 4-8.
Not Assigned.
Should be tied low.
NRZ Enable [H/W Mode].
0 = Bipolar data at RPOS/RNEG and TPOS/TNEG
1 = NRZ data at RPOS and TPOS or TNEG; RNEG outputs a
positive going pulse when device receives a BPV, CV, or EXZ.
PRBS Bit Error Output.
The receiver will constantly search for a
QRSS (T1) or a 2
15
-1 (E1) PRBS depending on whether T1 or E1
mode is selected. Remains high if out of synchronization with the
PRBS pattern. Goes low when synchronized to the PRBS pattern.
Any errors in the received pattern after synchronization will cause a
positive going pulse (with same period as E1 or T1 clock)
synchronous with RCLK.
Receive Clock.
Buffered recovered clock from the line.
Synchronous to MCLK in absence of signal at RTIP and RRING.
Receive Carrier Loss.
An output which will toggle high during a
receive carrier loss.
Receive Negative Data.
Updated on the rising edge (CES = 0) or
the falling edge (CES = 1) of RCLK with the bipolar data out of the
line interface. Set NRZE to a one for NRZ applications. In NRZ
mode, data will be output on RPOS while a received error will cause
a positive-going pulse synchronous with RCLK at RNEG. See
Section 8.4 for details.
Receive Positive Data.
Updated on the rising edge (CES = 0) or the
falling edge (CES = 1) of RCLK with bipolar data out of the line
interface. Set NRZE pin to a one for NRZ applications. In NRZ
mode, data will be output on RPOS while a received error will cause
a positive-going pulse synchronous with RCLK at RNEG. See
Section 8.4 for details.
Receive LIU Termination Select Bits 0 & 1 [H/W Mode].
These
inputs determine the receive termination. See Table 4-9.
Receive Tip and Ring.
Analog inputs for clock recovery circuitry.
These pins connect via a 1:1 transformer to the line. See Section 7
for details.
Receive & Transmit Synchronization Clock Enable.
0 = disable 2.048 MHz synchronization transmit and receive mode
1 = enable 2.048 MHz synchronization transmit and receive mode
MCLK
30
I
MM0/
MM1
18/
19
I
NA
NRZE
-
3
I
I
PBEO
24
O
RCLK
40
O
RCL
25
O
RNEG
39
O
RPOS
38
O
RT0/
RT1
RTIP/
RRING
44/
23
27/
28
I
I
SCLKE
4
I
相關(guān)PDF資料
PDF描述
DS2148G 5V E1/T1/J1 Line Interface
DS2148GN 5V E1/T1/J1 Line Interface
DS2148T 5V E1/T1/J1 Line Interface
DS2148TN 5V E1/T1/J1 Line Interface
DS21Q48 5V E1/T1/J1 Line Interface
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS2148DK 功能描述:網(wǎng)絡(luò)開發(fā)工具 DS2148 Dev Kit RoHS:否 制造商:Rabbit Semiconductor 產(chǎn)品:Development Kits 類型:Ethernet to Wi-Fi Bridges 工具用于評估:RCM6600W 數(shù)據(jù)速率:20 Mbps, 40 Mbps 接口類型:802.11 b/g, Ethernet 工作電源電壓:3.3 V
DS2148G 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS2148G+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 5V E1/T1/J1 Line Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS2148GB 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS2148GN 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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