
DS21455/DS21458 Quad T1/E1/J1 Transceivers
3 of 270
TABLE OF CONTENTS
1.
DESCRIPTION ................................................................................................................................................9
S
TANDARDS
...................................................................................................................... 10
FEATURE HIGHLIGHTS...............................................................................................................................11
G
ENERAL
.......................................................................................................................... 11
L
INE
I
NTERFACE
................................................................................................................ 11
C
LOCK
S
YNTHESIZER
........................................................................................................ 11
J
ITTER
A
TTENUATOR
......................................................................................................... 12
F
RAMER
/F
ORMATTER
........................................................................................................ 12
S
YSTEM
I
NTERFACE
........................................................................................................... 13
HDLC C
ONTROLLERS
....................................................................................................... 13
T
EST AND
D
IAGNOSTICS
.................................................................................................... 13
E
XTENDED
S
YSTEM
I
NFORMATION
B
US
.............................................................................. 14
2.10
C
ONTROL
P
ORT
................................................................................................................ 14
3.
BLOCK DIAGRAM........................................................................................................................................15
4.
DS21455/DS21458 DELTA...........................................................................................................................17
4.1
P
ACKAGE
.......................................................................................................................... 17
4.2
C
ONTROLLER
I
NTERFACE
................................................................................................... 17
4.3
ESIB F
UNCTION
................................................................................................................ 17
4.4
F
RAMER
/LIU I
NTERIM
S
IGNALS
.......................................................................................... 17
5.
PIN FUNCTION DESCRIPTION....................................................................................................................20
5.1
T
RANSMIT
S
IDE
P
INS
......................................................................................................... 20
5.2
R
ECEIVE
S
IDE
P
INS
........................................................................................................... 22
5.3
P
ARALLEL
C
ONTROL
P
ORT
P
INS
........................................................................................ 24
5.4
E
XTENDED
S
YSTEM
I
NFORMATION
B
US
.............................................................................. 26
5.5
JTAG T
EST
A
CCESS
P
ORT
P
INS
........................................................................................ 26
5.6
L
INE
I
NTERFACE
P
INS
........................................................................................................ 27
5.7
S
UPPLY
P
INS
.................................................................................................................... 28
5.8
P
IN
D
ESCRIPTIONS
............................................................................................................ 29
5.9
P
ACKAGES
........................................................................................................................ 39
6.
PARALLEL PORT.........................................................................................................................................41
6.1
R
EGISTER
M
AP
................................................................................................................. 41
7.
SPECIAL PER-CHANNEL REGISTER OPERATION..................................................................................46
8.
PROGRAMMING MODEL.............................................................................................................................48
8.1
P
OWER
-U
P
S
EQUENCE
...................................................................................................... 49
8.1.1
Master Mode Register
........................................................................................................49
8.2
I
NTERRUPT
H
ANDLING
....................................................................................................... 50
8.3
S
TATUS
R
EGISTERS
.......................................................................................................... 50
8.4
I
NFORMATION
R
EGISTERS
.................................................................................................. 51
8.5
I
NTERRUPT
I
NFORMATION
R
EGISTERS
................................................................................ 51
9.
CLOCK MAP .................................................................................................................................................52
10.
T1 FRAMER/FORMATTER CONTROL REGISTERS .................................................................................53
10.1
T1 C
ONTROL
R
EGISTERS
.................................................................................................. 53
10.2
T1 T
RANSMIT
T
RANSPARENCY
........................................................................................... 58
10.3
AIS-CI
AND
RAI-CI G
ENERATION AND
D
ETECTION
............................................................. 59
10.4
T1 R
ECEIVE
-S
IDE
D
IGITAL
-M
ILLIWATT
C
ODE
G
ENERATION
................................................. 60
10.5
T1 I
NFORMATION
R
EGISTER
............................................................................................... 62
11.
E1 FRAMER/FORMATTER CONTROL REGISTERS.................................................................................64
11.1
E1 C
ONTROL
R
EGISTERS
.................................................................................................. 64
11.2
A
UTOMATIC
A
LARM
G
ENERATION
....................................................................................... 68
11.2.1
Auto AIS
...........................................................................................................................68
11.2.2
Auto RAI
...........................................................................................................................68
11.2.3
Auto E-Bit
.........................................................................................................................68
11.2.4
G.706 CRC-4 Interworking
............................................................................................68
11.3
E1 I
NFORMATION
R
EGISTERS
............................................................................................ 69
12.
COMMON CONTROL AND STATUS REGISTERS.....................................................................................71
1.1
2.
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9