參數(shù)資料
型號: DS21372T+
廠商: Maxim Integrated Products
文件頁數(shù): 22/22頁
文件大?。?/td> 0K
描述: IC TESTER BIT ERROR 3.3V 32-TQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 250
功能: 位誤碼率測試器(BERT)
接口: T1
電路數(shù): 1
電源電壓: 3 V ~ 3.6 V
電流 - 電源: 10mA
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 32-TQFP
供應(yīng)商設(shè)備封裝: 32-TQFP(7x7)
包裝: 托盤
包括: 錯(cuò)誤計(jì)數(shù)器,樣式發(fā)生器和檢測器
產(chǎn)品目錄頁面: 1430 (CN2011-ZH PDF)
DS21372
9 of 22
7. ERROR INSERT REGISTER
The Error Insertion Register (EIR) controls circuitry within the DS21372 that allows the generated
pattern to be intentionally corrupted. Bit errors can be inserted automatically at regular intervals by
properly programming the EIR0 to EIR2 bits or bit errors can be inserted at random (under
microcontroller control) via the EIR.3 bit.
EIR: ERROR INSERT REGISTER (ADDRESS=07 HEX)
(MSB)
(LSB)
-
TINV
RINV
SBE
EIR2
EIR1
EIR0
SYMBOL
POSITION
NAME AND DESCRIPTION
-EIR.7
Not Assigned. Should be set to 0 when written to.
-EIR.6
Not Assigned. Should be set to 0 when written to.
TINV
EIR.5
Transmit Data Inversion Select.
0 = do not invert data to be transmitted at TDATA
1 = invert data to be transmitted at TDATA
RINV
EIR.4
Receive Data Inversion Select.
0 = do not invert data received at RDATA
1 = invert data received at RDATA
SBE
EIR.3
Single Bit Error Insert. A low to high transition will create a
single bit error. Must be cleared and set again for a subsequent
bit error to be inserted. Can be used to accomplish rates not
addressed in Table 3 (e.g., BER of less than 10
-7).
EIB2
EIR.2
Error Insert Bit 2. See Table 3.
EIB1
EIR.1
Error Insert Bit 1. See Table 3.
EIB0
EIR.0
Error Insert Bit 0. See Table 3.
ERROR BIT INSERTION Table 3
EIB2
EIB1
EIB0
ERROR RATE INSERTED
0
no errors automatically inserted
00
1
10
-1
01
0
10
-2
01
1
10
-3
10
0
10
-4
10
1
10
-5
11
0
10
-6
11
1
10
-7
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