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參數(shù)資料
| 型號： | DS21372 |
| 英文描述： | 3.3V Bit Error Rate Tester BERT |
| 中文描述： | 3.3V、位誤碼率測試器(BERT) |
| 文件頁數(shù)： | 8/21頁 |
| 文件大?。?/td> | 214K |
| 代理商： | DS21372 |
DS21372
8 of 21
6.
The Pattern Control Register (PCR) is used to configure the operating parameters of the DS21372 and to
control the patterns being generated and received. Also the PCR is used to control the pattern
synchronizer and the error and bit counters.
PATTERN CONTROL REGISTER
PCR: PATTERN CONTROL REGISTER
(ADDRESS=06 HEX)
(MSB) (LSB)
TL
QRSS
PS
LC
RL
SYNCE
RESYNC
LPBK
SYMBOL
POSITION
NAME AND DESCRIPTION
TL
PCR.7
Transmit Load.
A low to high transition loads the pattern
generator with the contents of the Pattern Set Registers. PCR.7 is
logically ORed with the input pin TL. Must be cleared and set
again for subsequent loads.
QRSS
PCR.6
Zero Suppression Select.
Forces a 1 into the pattern whenever
the next 14 bit positions are all 0s. Should only be set when
using the QRSS pattern.
0 = Zero suppression disabled
1 = Zero suppression enabled
PS
PCR.5
Pattern Select.
0 = Repetitive Pattern
1 = Pseudorandom Pattern
LC
PCR.4
Latch Count Registers.
A low to high transition latches the bit
and error counts into the user accessible registers BCR and
BECR and clears the internal register count. PCR.4 is logically
OR’ed with input pin LC. Must be cleared and set again for
subsequent loads.
RL
PCR.3
Receive Data Load.
A transition from low to high loads the
previous 32 bits of data received at RDATA into the Pattern
Receive Registers (PRR). PCR.3 is logically OR’ed with input
pin RL. Must be cleared and set again for subsequent latches.
SYNCE
PCR.2
SYNC Enable.
0 = auto resync is enabled.
1 = auto resync is disabled.
RESYNC
PCR.1
Initiate Manual Resync Process.
A low to high transition will
force the DS21372 to resynchronize to the incoming pattern at
RDATA. Must be cleared and set again for a subsequent resync.
LPBK
PCR.0
Transmit/Receive Loopback Select.
When enabled, the
RDATA input is disabled; TDATA continues to output data as
normal. See Figure 1.
0 = loopback disabled
1 = loopback enabled
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PDF描述 |
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| DS21372T | 3.3V Bit Error Rate Tester BERT |
| DS21372TN | 3.3V Bit Error Rate Tester BERT |
| DS2141A | T1 Controller |
| DS2143 | E1/ISDN-PRI framing transceiver |
| DS2143Q | E1/ISDN-PRI framing transceiver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS21372T | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3V Bit Error Rate Tester (BERT) RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21372T+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3V Bit Error Rate Tester (BERT) RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21372TN | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3V Bit Error Rate Tester (BERT) RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21372TN+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3V Bit Error Rate Tester (BERT) RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS214 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
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