- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄10993 > DS21352G (Maxim Integrated Products)IC TXRX T1 1-CHIP 3.3V 100-BGA PDF資料下載
參數(shù)資料
| 型號： | DS21352G |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 83/137頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX T1 1-CHIP 3.3V 100-BGA |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 240 |
| 功能： | 單芯片收發(fā)器 |
| 接口： | HDLC，T1 |
| 電路數(shù)： | 1 |
| 電源電壓： | 3.14 V ~ 3.47 V |
| 電流 - 電源： | 75mA |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 100-CSBGA（10x10） |
| 包裝： | 托盤 |
| 包括： | DSX-1 和 CSU 線路補(bǔ)償發(fā)生器，HDLC 控制器，帶內(nèi)回路代碼發(fā)生器和檢測器 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁當(dāng)前第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁
DS21352/DS21552
5 of 137
1. LIST OF FIGURES
Figure 3-1 SCT BLOCK DIAGRAM.........................................................................................................9
Figure 16-1 EXTERNAL ANALOG CONNECTIONS ..........................................................................87
Figure 16-2 OPTIONAL CRYSTAL CONNECTIONS ..........................................................................88
Figure 16-3 TRANSMIT WAVEFORM TEMPLANE............................................................................89
Figure 16-4 JITTER TOLERANCE.........................................................................................................91
Figure 16-5 JITTER ATTENUATION ....................................................................................................91
Figure 16-6 PROTECTED INTERFACE EXAMPLE FOR THE DS21552...........................................93
Figure 16-7 PROTECTED INTERFACE EXAMPLE FOR TE DS21352..............................................94
Figure 16-8 TYPICAL MONITOR PORT APPLICATION....................................................................95
Figure 19-1 JTAG FUNCTIONAL BLOCK DIAGRAM......................................................................100
Figure 19-2 TAP CONTROLLER STATE DIAGRAM ........................................................................103
Figure 20-1 IBO BASIC CONFIGURATION USING 4 SCTS ............................................................110
Figure 21-1 RECEIVE SIDE D4 TIMING.............................................................................................111
Figure 21-2 RECEIVE SIDE ESF TIMING...........................................................................................112
Figure 21-3 RECEIVE SIDE BOUNDARY TIMING (with elastic store disabled)..............................113
Figure 21-4 RECEIVE SIDE 1.544 MHz BOUNDARY TIMING (with elastic store enabled) ...........113
Figure 21-5 RECEIVE SIDE 2.048 MHz BOUNDARY TIMING (with elastic store enabled) ...........114
Figure 21-6 RECEIVE SIDE INTERLEAVE BUS OPERATION, BYTE MODE ..............................115
Figure 21-7 RECEIVE SIDE INTERLEAVE BUS OPERATION, FRAME MODE...........................116
Figure 21-8 TRANSMIT SIDE D4 TIMING.........................................................................................117
Figure 21-9 TRANSMIT SIDE ESF TIMING.......................................................................................118
Figure 21-10 TRANSMIT SIDE BOUNDARY TIMING (with elastic store disabled) ........................119
Figure 21-11 TRANSMIT SIDE 1.544 MHz BOUNDARY TIMING (with elastic store enabled)......119
Figure 21-12 TRANSMIT SIDE 2.048 MHz BOUNDARY TIMING (with elastic store enabled)......120
Figure 21-13 TRANSMIT SIDE INTERLEAVE BUS OPERATION, BYTE MODE.........................121
Figure 21-14 TRANSMIT SIDE INTERLEAVE BUS OPERATION, FRAME MODE .....................122
Figure 22-1 RECEIVE DATA FLOW ...................................................................................................123
Figure 22-2 TRANSMIT DATA FLOW................................................................................................124
Figure 24-1 INTEL BUS READ TIMING (BTS=0 / MUX=1) .............................................................127
Figure 24-2 INTEL BUS WRITE TIMING (BTS=0 / MUX=1) ...........................................................127
Figure 24-3 MOTOROLA BUS TIMING (BTS=1 / MUX=1)..............................................................128
Figure 24-4 INTEL BUS READ TIMING (BTS=0 / MUX=0) ..............................................................130
Figure 24-5 INTEL BUS READ TIMING (BTS=0 / MUX=0) .............................................................130
Figure 24-6 MOTOROLA BUS READ TIMING (BTS=1 / MUX=0)..................................................131
Figure 24-7 MOTOROLA BUS READ TIMING (BTS=1 / MUX=0)..................................................131
Figure 24-8 RECEIVE SIDE TIMING ..................................................................................................133
Figure 24-9 RECEIVE SIDE TIMING, ELASTIC STORE ENABLED...............................................134
Figure 24-10 RECEIVE LINE INTERFACE TIMING .........................................................................135
Figure 24-11 TRANSMIT SIDE TIMING.............................................................................................137
Figure 24-12 TRANSMIT SIDE TIMING, ELASTIC STORE ENABLED .........................................138
Figure 24-13 TRANSMIT LINE INTERFACE TIMING......................................................................138
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS2174QN+T&R | IC BERT ENHANCED 44-PLCC |
| DS2155GNC2+T&R | TXRX T1/E1/J1 SGL 100CSBGA |
| DS2155GNC2+ | IC TXRX T1/E1/J1 100-CSBGA |
| DS2155GN | IC TXRX T1/E1/J1 1-CHIP 100CSBGA |
| DS2174Q+ | IC BERT ENHANCED 44-PLCC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS21352GN | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21352L | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC T1 Single Chip Transceivers RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21352L+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC T1 Single Chip Transceivers RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21352LB | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC T1 Single Chip Transceivers RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21352LB+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC T1 Single Chip Transceivers RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。