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參數(shù)資料
| 型號(hào)： | DS1992 |
| 英文描述： | 1kb/4kb Memory iButton |
| 中文描述： | 1K位/4K位存儲(chǔ)器iButton® |
| 文件頁(yè)數(shù)： | 10/17頁(yè) |
| 文件大?。?/td> | 223K |
| 代理商： | DS1992 |
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DS1992/DS1993
1-WIRE BUS SYSTEM
The 1-Wire bus is a system that has a single bus master and one or more slaves. In all instances the
DS199_ is a slave device. The bus master is typically a microcontroller or PC. For small configurations
the 1-Wire communication signals can be generated under software control using a single port pin. For
multisensor networks, the DS2480B 1-Wire line driver chip or serial port adapters based on this chip
(DS9097U series) are recommended. This simplifies the hardware design and frees the microprocessor
from responding in real-time.
10of 10
The discussion of this bus system is broken down into three topics: hardware configuration, transaction
sequence, and 1-Wire signaling (signal types and timing). The 1-Wire protocol defines bus transactions in
terms of the bus state during specific time slots that are initiated on the falling edge of sync pulses from
the bus master. For a more detailed protocol description, refer to Chapter 4 of the
Book of DS19xx iButton
Standards
.
HARDWARE CONFIGURATION
The 1-Wire bus has only a single line by definition; it is important that each device on the bus be able to
drive it at the appropriate time. To facilitate this, each device attached to the 1-wire bus must have open-
drain or three-state outputs. The 1-Wire port of the DS199_ is open drain with an internal circuit
equivalent to that shown in Figure 8. A multidrop bus consists of a 1-Wire bus with multiple slaves
attached. The 1-Wire bus has a maximum data rate of 16.3kbps and requires a pullup resistor of
approximately 5k . The idle state for the 1-Wire bus is high. If for any reason a transaction needs to be
suspended, the bus
must
be left in the idle state if the transaction is to resume. If this does not occur and
the bus is left low for more than 120 s, one or more of the devices on the bus may be reset.
Figure 8. HARDWARE CONFIGURATION
Open Drain
Port Pin
RX = RECEIVE
TX = TRANSMIT
100
MOSFET
V
PUP
RX
TX
TX
RX
DATA
R
PU
5 μA
Typ.
BUS MASTER
DS199X 1-Wire PORT
TRANSACTION SEQUENCE
The protocol for accessing the DS199_ through the 1-Wire port is as follows:
Initialization
ROM Function Command
Memory Function Command
Transaction/Data
INITIALIZATION
All transactions on the 1-wire bus begin with an initialization sequence. The initialization sequence
consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS1993 | 1kb/4kb Memory iButton |
| DS1992L-F5 | 1kbit/4kbit Memory iButtonTM DS1994 4-kbit Plus Time Memory iButtonTM |
| DS21349DK | T1/J1 Line Interface Unit Design Kit |
| DS2149DK | T1/J1 Line Interface Unit Design Kit |
| DS21349 | 3.3V T1/J1 Line Interface Unit |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS1992_11 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:1Kb/4Kb Memory iButton 1024 bits of Read/Write Nonvolatile |
| DS1992L | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| DS1992L+F5 | 制造商:Maxim Integrated Products 功能描述:IC MEMORY I BUTTON 1992 |
| DS1992L-E00 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:(135.97 k) |
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