
DS1986
052298 14/24
A multidrop bus consists of a 1–Wire bus with multiple
slaves attached. At regular speed the 1–Wire bus has a
maximum data rate of 16.3k bits per second. The speed
can be boosted to 142k bits per second by activating the
Overdrive mode. If the bus master is also required to
perform programming of the EPROM portions of the
DS1986, a programming supply capable of delivering
up to 10 milliamps at 12 volts for 480
μ
s is required. The
idle state for the 1–Wire bus is high. If, for any reason, a
transaction needs to be suspended, the bus MUST be
left in the idle state if the transaction is to resume. If this
does not occur and the bus is left low for more than 16
μ
s
(overdrive speed) or more than 120
μ
s (regular speed),
one or more of the devices on the bus may be reset.
Transaction Sequence
The sequence for accessing the DS1986 via the 1–Wire
port is as follows:
Initialization
ROM Function Command
Memory Function Command
Read/Write Memory/Status
INITIALIZATION
All transactions on the 1–Wire bus begin with an initial-
ization sequence. The initialization sequence consists
of a reset pulse transmitted by the bus master followed
by a presence pulse(s) transmitted by the slave(s).
The presence pulse lets the bus master know that the
DS1986 is on the bus and is ready to operate. For more
details, see the “1–Wire Signalling” section.
ROM FUNCTION COMMANDS
Once the bus master has detected a presence, it can
issue one of the six ROM function commands. All ROM
function commands are eight bits long. A list of these
commands follows (refer to flowchart in Figure 8):
Read ROM [33H]
This command allows the bus master to read the
DS1986’s 8–bit family code, unique 48–bit serial num-
ber, and 8–bit CRC. This command can be used only if
there is a single DS1986 on the bus. If more than one
slave is present on the bus, a data collision will occur
when all slaves try to transmit at the same time (open
drain will produce a wired–AND result). The resultant
family code and 48–bit serial number will usually result
in a mismatch of the CRC.
Match ROM [55H]
The match ROM command, followed by a 64–bit ROM
sequence, allows the bus master to address a specific
DS1986 on a multidrop bus. Only the DS1986 that
exactly matches the 64–bit ROM sequence will respond
to the subsequent memory function command. All
slaves that do not match the 64–bit ROM sequence will
wait for a reset pulse. This command can be used with a
single or multiple devices on the bus.
Skip ROM [CCH]
This command can save time in a single drop bus sys-
tem by allowing the bus master to access the memory
functions without providing the 64–bit ROM code. If
more than one slave is present on the bus and a read
command is issued following the Skip ROM command,
data collision will occur on the bus as multiple slaves
transmit simultaneously (open drain pull–downs will
produce a wired–AND result).
Search ROM [F0H]
When a system is initially brought up, the bus master
might not know the number of devices on the 1–Wire
bus or their 64–bit ROM codes. The search ROM com-
mand allows the bus master to use a process of elimina-
tion to identify the 64–bit ROM codes of all slave devices
on the bus. The ROM search process is the repetition of
a simple 3–step routine: read a bit, read the complement
of the bit, then write the desired value of that bit. The bus
master performs this simple, 3–step routine on each bit
of the ROM. After one complete pass, the bus master
knows the contents of the ROM in one device. The
remaining number of devices and their ROM codes may
be identified by additional passes. See Chapter 5 of the
Book of DS19xx iButton Standards for a comprehensive
discussion of a ROM search, including an actual exam-
ple.