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參數(shù)資料
| 型號： | DS1986 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | 64K bit Add-Only iButton(64K位只加按鈕) |
| 中文描述： | 64K位只添加iButton® |
| 文件頁數(shù)： | 13/24頁 |
| 文件大?。?/td> | 164K |
| 代理商： | DS1986 |
DS1986
052298 13/24
WRITE MEMORY [0FH]/SPEED WRITE
MEMORY [F3H]
The Write Memory command is used to program the
65536–bit EPROM data field. The details of the func-
tional flow chart are described in the section “WRITING
EPROM MEMORY”.
The data memory address range is 0000H to 1FFFH. If
the bus master sends a starting address higher than
this, the three most significant address bits are set to
zeros by the internal circuitry of the chip. This will result
in a mismatch between the CRC calculated by the
DS1986 and the CRC calculated by the bus master,
indicating an error condition.
To save time when writing more than one consecutive
byte of the DS1986’s data memory it is possible to omit
reading the 16–bit CRC which allows verification of data
and address before the data is copied to the EPROM
memory. At regular speed this saves 16 time slots or
976
μ
s for every byte to be programmed. This speed–
programming mode is accessed with the command
code F3H instead of 0FH. It follows basically the same
flow chart as the Write Memory command, but skips
sending the CRC immediately preceding the program
pulse. This command should only be used if the electri-
cal contact between bus master and the DS1986 is firm
since a poor contact may result in corrupted data inside
the EPROM memory.
WRITE STATUS [55H]/ SPEED WRITE
STATUS [F5H]
The Write Status command is used to program the
2816–bit EPROM Status Memory field. The details of
the functional flow chart are described in the section
“WRITING EPROM MEMORY”.
The Status Memory address range is 0000H to 01FFH.
Attempts to write to the not implemented status memory
locations will be ignored. If the bus master sends a start-
ing address higher than 1FFFH, the three most signifi-
cant address bits are set to zeros by the internal circuitry
of the chip. This will result in a mismatch between the
CRC calculated by the DS1986 and the CRC calculated
by the bus master, indicating an error condition.
To save time when writing more than one consecutive
byte of the DS1986’s status memory it is possible to omit
reading the 16–bit CRC which allows verification of data
and address before the data is copied to the EPROM
memory. At regular speed this saves 16 time slots or
976
μ
s for every byte to be programmed. This speed–
programming mode is accessed with the command
code F5H instead of 55H. It follows basically the same
flow chart as the Write Status command, but skips send-
ing the CRC immediately preceding the program pulse.
This command should only be used if the electrical con-
tact between bus master and the DS1986 is firm since a
poor contact may result in corrupted data inside the
EPROM status memory.
1–WIRE BUS SYSTEM
The 1–Wire bus is a system which has a single bus mas-
ter and one or more slaves. In all instances, the DS1986
is a slave device. The bus master is typically a micro-
controller. The discussion of this bus system is broken
down into three topics: hardware configuration, transac-
tion sequence, and 1–Wire signalling (signal type and
timing). A 1–Wire protocol defines bus transactions in
terms of the bus state during specified time slots that are
initiated on the falling edge of sync pulses from the bus
master. For a more detailed protocol description, refer to
Chapter 4 of the Book of DS19xx iButton Standards.
Hardware Configuration
The 1–Wire bus has only a single line by definition; it is
important that each device on the bus be able to drive it
at the appropriate time. To facilitate this, each device
attached to the 1–Wire bus must have an open drain
connection or 3–state outputs. The DS1986 is an open
drain part with an internal circuit equivalent to that
shown in Figure 6. The bus master can be the same
equivalent circuit. If a bidirectional pin is not available,
separate output and input pins can be tied together.
The bus master requires a pull–up resistor at the master
end of the bus, with the bus master circuit equivalent to
the one shown in Figures 7a and 7b. The value of the
pull–up resistor should be approximately 5k
for short
line lengths.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS1986+F3 | 制造商:Maxim Integrated Products 功能描述:ADD-O IBTN 64KB, F3 (GENERIC) LFREE - Rail/Tube |
| DS19860-F3-W | 功能描述:iButton RoHS:否 存儲類型:SRAM 存儲容量:512 B 組織: 工作電源電壓:3 V to 5.25 V 接口類型:1-Wire 最大工作溫度:+ 85 C 尺寸:17.35 mm x 5.89 mm 封裝 / 箱體:F5 MicroCan 制造商:Maxim Integrated |
| DS1986-F3 | 功能描述:iButton RoHS:否 存儲類型:SRAM 存儲容量:512 B 組織: 工作電源電壓:3 V to 5.25 V 接口類型:1-Wire 最大工作溫度:+ 85 C 尺寸:17.35 mm x 5.89 mm 封裝 / 箱體:F5 MicroCan 制造商:Maxim Integrated |
| DS1986-F3# | 功能描述:iButton RoHS:否 存儲類型:SRAM 存儲容量:512 B 組織: 工作電源電壓:3 V to 5.25 V 接口類型:1-Wire 最大工作溫度:+ 85 C 尺寸:17.35 mm x 5.89 mm 封裝 / 箱體:F5 MicroCan 制造商:Maxim Integrated |
| DS1986-F3+ | 功能描述:iButton RoHS:否 存儲類型:SRAM 存儲容量:512 B 組織: 工作電源電壓:3 V to 5.25 V 接口類型:1-Wire 最大工作溫度:+ 85 C 尺寸:17.35 mm x 5.89 mm 封裝 / 箱體:F5 MicroCan 制造商:Maxim Integrated |
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