
DS1923: Hygrochron Temperature/Humidity Logger iButton with 8kB Data Log Memory
Figure 10. HARDWARE CONFIGURATION
36 of 52
Open Drain
Port Pin
RX = RECEIVE
TX = TRANSMIT
100
MOSFET
V
PUP
RX
TX
TX
RX
DATA
5 μA
Typ.
BUS MASTER
DS1923 1-Wire PORT
R
PUP
TRANSACTION SEQUENCE
The protocol for accessing the DS1923 through the 1-Wire port is as follows:
Initialization
ROM Function Command
Memory/Control Function Command
Transaction/Data
INITIALIZATION
All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence consists of a
reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the slave(s). The presence
pulse lets the bus master know that the DS1923 is on the bus and is ready to operate. For more details, see the
1-Wire Signaling
section.
1-Wire ROM FUNCTION COMMANDS
Once the bus master has detected a presence, it can issue one of the eight ROM function commands that the
DS1923 supports. All ROM function commands are 8 bits long. A list of these commands follows (refer to flowchart
in Figure 11).
Read ROM [33h]
This command allows the bus master to read the DS1923’s 8-bit family code, unique 48-bit serial number, and 8-bit
CRC. This command can only be used if there is a single slave on the bus. If more than one slave is present on the
bus, a data collision occurs when all slaves try to transmit at the same time (open-drain produces a wired-AND
result). The resultant family code and 48-bit serial number results in a mismatch of the CRC.
Match ROM [55h]
The Match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address a specific
DS1923 on a multidrop bus. Only the DS1923 that exactly matches the 64-bit ROM sequence responds to the
following memory function command. All other slaves will wait for a reset pulse. This command can be used with a
single or multiple devices on the bus.
Search ROM [F0h]
When a system is initially brought up, the bus master might not know the number of devices on the 1-Wire bus or
their registration numbers. By taking advantage of the wired-AND property of the bus, the master can use a
process of elimination to identify the registration numbers of all slave devices. For each bit of the registration
number, starting with the least significant bit, the bus master issues a triplet of time slots. On the first slot, each
slave device participating in the search outputs the true value of its registration number bit. On the second slot,
each slave device participating in the search outputs the complemented value of its registration number bit. On the
third slot, the master writes the true value of the bit to be selected. All slave devices that do not match the bit
written by the master stop participating in the search. If both of the read bits are zero, the master knows that slave