參數(shù)資料
型號: DS1922T
英文描述: Temperature Logger iButton with 8kB Datalog Memory
文件頁數(shù): 33/48頁
文件大?。?/td> 428K
代理商: DS1922T
DS1922L/DS1922T
33 of 48
STOP MISSION WITH PASSWORD [33H]
The DS1922L/T uses a control function command to stop a mission. Only a mission that is in progress can be
stopped. After the command code, the master must transmit the 64-bit full-access password followed by a FFh
dummy byte. If passwords are enabled and the transmitted password is different from the stored full-access
password or a mission is not in progress, the Stop Mission with Password command will fail. The device will stop
communicating and will wait for a reset pulse. If the password was correct or if passwords were not enabled, the
device will clear the MIP bit in the General Status Register and restore write access to the Register Pages. The
WFTA bit is not cleared. See the description of the General Status Register for a method to clear the WFTA bit.
MEMORY ACCESS CONFLICTS
While a mission is in progress or while the device is waiting for a temperature alarm to start a mission, periodically
a temperature sample is taken and logged. This "internal activity" has priority over 1-Wire communication. As a
consequence, device-specific commands (excluding ROM function commands and 1-Wire reset) will not perform
properly when internal and "external" activities interfere with each other. Not affected are the commands Start
Mission, Forced Conversion and Clear Memory, because they are not applicable while a mission is in progress or
while the device is waiting for a temperature alarm. The table below explains how the remaining five commands are
affected by internal activity, how to detect this interference and how to work around it.
COMMAND
INDICATION OF
INTERFERENCE
REMEDY
Write Scratchpad
The CRC16 at the end of the
command flow reads FFFFh.
Wait 0.5 s, 1-Wire reset, address the device, repeat
Write Scratchpad with the same data and check the
validity of the CRC16 at the end of the command flow.
Alternatively, use Read Scratchpad to verify data
integrity.
Read Scratchpad
The data read changes to FFh
bytes or all bytes received are
FFh, including the CRC at the
end of the command flow.
The device behaves as if
Authorization Code or pass-
word was not valid or as if the
copy function would not end.
The data read changes to all
FFh bytes or all bytes received
are FFh, including the CRC at
the end of the command flow,
despite a valid password.
Wait 0.5s, 1-Wire reset, address the device, repeat
Read Scratchpad and check the validity of the CRC16
at the end of the command flow.
Copy Scratchpad
Wait 0.5s, 1-Wire reset, address the device, issue
Read Scratchpad and check the AA-bit of the E/S byte.
If the AA-bit is set, Copy Scratchpad was successful.
Read Memory with
CRC
Wait 0.5s, 1-Wire reset, address the device, repeat
Read Memory with CRC and check the validity of the
CRC16 at the end of the memory page.
Stop Mission
The general Status register at
address 215h reads FFh or the
MIP bit is 1 while bits 0, 2, and
5 are 0.
Wait 0.5s, 1-Wire reset, address the device, and
repeat Stop Mission. Perform a 1-Wire reset, address
the device, read the general Status register at address
215h and check the MIP-bit. If the MIP-bit is 0, Stop
Mission was successful.
The interference is more likely to be seen with a high sample rate (1 sample every second) and with high-resolution
logging, which can last up to 600ms. With lower sample rates interference may hardly be visible at all. In any case,
when writing driver software, it is important to know about the possibility of interference and to take measures to
work around it.
1-Wire BUS SYSTEM
The 1-Wire bus is a system, which has a single bus master and one or more slaves. In all instances the DS1922L/T
is a slave device. The bus master is typically a microcontroller. The discussion of this bus system is broken down
into three topics: hardware configuration, transaction sequence, and 1-Wire signaling (signal types and timing). The
1-Wire protocol defines bus transactions in terms of the bus state during specific time slots that are initiated on the
falling edge of sync pulses from the bus master. For a more detailed protocol description, refer to Chapter 4 of the
Book of DS19xx iButton Standards
.
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