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參數(shù)資料
| 型號： | DS1878T+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 9/101頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CTLR SFP W/DGTL LDD RX 28TQFN |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 類型： | SFP+ 控制器 |
| 輸入類型： | 模擬，數(shù)字 |
| 輸出類型： | 數(shù)字 |
| 接口： | I²C，LDD，串行 |
| 電流 - 電源： | 2.5mA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-WFQFN 裸露焊盤 |
| 供應商設備封裝： | 28-TQFN-EP（5x5） |
| 包裝： | 帶卷 (TR) |
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temperature, so the tINIT time is not required for the device
to recall the APC and MOD set points from EEPROM.
BIAS and MODULATION Registers as a
Function of Transmit Disable (TXD)
If TXD is asserted (logic 1) during normal operation,
the 3-wire master writes the laser driver bias and
MODULATION DACs to 0. When TXD is deasserted
(logic 0), the device sets the MODULATION register
with the value associated with the present temperature,
and initializes the BIAS register using the same search
algorithm as done at startup. When asserted, soft TXD
(TXDC) (Lower Memory, Register 6Eh) would allow a
software control identical to the TXD pin (see Figure 3).
APC and Quick-Trip Timing
As shown in Figure 4, the device’s input comparator is
shared between the APC control loop and the quick-
trip alarms (TXP HI, TXP LO, LOS, BIAS HI, and IBIAS
MAX). The comparator polls the alarms in a multiplexed
sequence. Five of every eight comparator readings are
used for APC loop bias-current control. The other three
updates are used to check the HTXP/LTXP (monitor
diode voltage), the HBATH (MON1), and LOS (MON3)
signals against the internal APC, BIAS, and MON3 ref-
erence, respectively. If the last APC comparison was
higher than the APC set point, it makes an HTXP com-
parison, and if it is lower, it makes an LTXP compari-
son. Depending on the results of the comparison, the
corresponding alarms and warnings (TXP HI, TXP LO)
are asserted or deasserted.
The device has a programmable comparator sample
time based on an internally generated clock to facilitate
a wide variety of external filtering options and time
delays resulting from writing values to the laser driver’s
bias DAC. The SAMPLE RATE register (Table 02h,
Register 88h) determines the sampling time. Samples
occur at a regular interval, tREP. Table 2 shows the
sample rate options available. Any quick-trip alarm that
is detected by default remains active until a subse-
quent comparator sample shows the condition no
longer exists. A second bias current monitor (BIAS
MAX) compares a Maxim laser driver’s BIAS DAC’s
code to a digital value stored in the IBIASMAX register.
This comparison is made at every bias current update
to ensure that a high-bias current is quickly detected.
DS1878
SFP+ Controller with Digital LDD Interface
______________________________________________________________________________________
15
APC QUICK-TRIP SAMPLE TIMES
HBIAS
SAMPLE
HBIAS
SAMPLE
LOS
SAMPLE
APC
SAMPLE
APC
SAMPLE
APC
SAMPLE
APC
SAMPLE
APC
SAMPLE
APC
SAMPLE
HTXP/LTXP
SAMPLE
tREP
Figure 4. APC Loop and Quick-Trip Sample Timing
Table 2. Update Rate Timing
APC_SR[2:0]
SAMPLE PERIOD (tREP)
(ns)
000b
800
001b
1200
010b
1600
011b
2000
100b
2800
101b
3200
110b
4400
111b
6400
tOFF
tON
TXD
TXDOUT
Figure 3. TXD Timing
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