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參數(shù)資料
| 型號： | DS1878T+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 44/101頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CTLR SFP W/DGTL LDD RX 28TQFN |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | SFP+ 控制器 |
| 輸入類型： | 模擬，數(shù)字 |
| 輸出類型： | 數(shù)字 |
| 接口： | I²C，LDD，串行 |
| 電流 - 電源： | 2.5mA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 28-TQFN-EP（5x5） |
| 包裝： | 帶卷 (TR) |
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DS1878
SFP+ Controller with Digital LDD Interface
______________________________________________________________________________________
47
Lower Memory, Register 71h: ALARM2
POWER-ON VALUE
00h
READ ACCESS
All
WRITE ACCESS
N/A
MEMORY TYPE
Volatile
71h
MON3 HI
MON3 LO
MON4 HI
MON4 LO
RESERVED
TXFS
FETG
TXFINT
BIT 7
BIT 0
BIT 7
MON3 HI: High-alarm status for MON3 measurement. A TXD event does not clear this alarm.
0 = (Default) Last measurement was equal to or below threshold setting.
1 = Last measurement was above threshold setting.
BIT 6
MON3 LO: Low-alarm status for MON3 measurement. A TXD event does not clear this alarm.
0 = (Default) Last measurement was equal to or above threshold setting.
1 = Last measurement was below threshold setting.
BIT 5
MON4 HI: High-alarm status for MON4 measurement. A TXD event does not clear this alarm.
0 = (Default) Last measurement was equal to or below threshold setting.
1 = Last measurement was above threshold setting.
BIT 4
MON4 LO: Low-alarm status for MON4 measurement. A TXD event does not clear this alarm.
0 = (Default) Last measurement was equal to or above threshold setting.
1 = Last measurement was below threshold setting.
BIT 3
RESERVED
BIT 2
TXFS: Reflects the status of the TXF pin. The status also includes any inversion caused by the INVTXF
bit (read only).
0 = TXF pin is low (after any inversion caused by the INVTXF bit).
1 = TXF pin is high (after any inversion caused by the INVTXF bit).
BIT 1
FETG: Status of Internal Signal FETG. The FETG signal is part of the internal shutdown logic.
0 = FETG is low.
1 = FETG is high.
BIT 0
TXFINT: TXFOUT Interrupt. This bit is the wire-ORed logic of all alarms and warnings wire-ANDed with
their corresponding enable bits in addition to nonmaskable alarms TXP HI, TXP LO, BIAS MAX, and HBAL.
The enable bits are found in Table 01h/05h, Registers F8h–FFh.
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