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參數(shù)資料
| 型號(hào)： | DS1855E-050+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 18/21頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RES TEMP-CNTRL 10/50K 14TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 接片： | 100，256 |
| 電阻（歐姆）： | 10k，50k，100k |
| 電路數(shù)： | 2 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 750 ppm/°C |
| 存儲(chǔ)器類型： | 非易失 |
| 接口： | I²C（設(shè)備位址） |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-TSSOP |
| 包裝： | 帶卷 (TR) |
DS1855
6 of 21
2-WIRE OPERATION
Clock and Data Transitions
The SDA pin is normally pulled high with an external resistor or device. Data on the SDA pin may only
change during SCL low time periods. Data changes during SCL high periods will indicate a START or
STOP conditions depending on the conditions discussed below. Refer to the timing diagram in Figure 2
for further details.
START Condition
A high-to-low transition of SDA with SCL high is a START condition that must precede any other
command. Refer to the timing diagram in Figure 2 for further details.
STOP Condition
A low-to-high transition of SDA with SCL high is a STOP condition. After a read sequence, the stop
command places the DS1855 into a low-power mode. Refer to the timing diagram in Figure 2 for further
details.
Acknowledge
All address and data bytes are transmitted via a serial protocol. The DS1855 pulls the SDA line low
during the ninth clock pulse to acknowledge that it has received each word.
Standby Mode
The DS1855 features a low-power mode that is automatically enabled after power-on, after a STOP
command, and after the completion of all internal operations.
2-Wire Interface Reset
After any interruption in protocol, power loss, or system reset, the following steps reset the DS1855:
1. Clock up to nine cycles.
2. Look for SDA high in each cycle while SCL is high.
3. Create a START condition while SDA is high.
Device Addressing
The DS1855 must receive an 8-bit device address word following a START condition to enable a specific
device for a read or write operation. The address word is clocked into the DS1855 MSB to LSB. The
address word consists of Ah (1010) followed by A2, A1, and A0 then the read/write (R/W) bit. If the
R/W bit is high, a read operation is initiated. If the R/W is low, a write operation is initiated. For a device
to become active, the values of A2, A1, and A0 must be the same as the hard-wired address pins on the
DS1855. Upon a match of written and hard-wired addresses, the DS1855 will output a zero for one clock
cycle as an acknowledge. If the address does not match, the DS1855 returns to a low-power mode.
Write Operations
After receiving a matching address byte with the R/W bit set low, the device goes into the write mode of
operation. The master must transmit an 8-bit EEPROM memory address to the device to define the
address where the data is to be written. After the reception of this byte, the DS1855 will transmit a zero
for one clock cycle to acknowledge the receipt of the address. The master must then transmit an 8-bit data
word to be written into this address. The DS1855 will again transmit a zero for one clock cycle to
acknowledge the receipt of the data. At this point, the master must terminate the write operation with a
STOP condition. The DS1855 then enters an internally timed write process Tw to the EEPROM memory.
All inputs are disabled during this byte write cycle.
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