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參數(shù)資料
| 型號： | DS1805E-010+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 9/10頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC POT DIG ADDRESS 10K 14-TSSOP |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 1,000 |
| 接片： | 256 |
| 電阻（歐姆）： | 10k |
| 電路數(shù)： | 1 |
| 溫度系數(shù)： | 標準值 550 ppm/°C |
| 存儲器類型： | 易失 |
| 接口： | I²C（設備位址） |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 14-TSSOP |
| 包裝： | 帶卷 (TR) |
DS1805
Addressable Digital Potentiometer
8
_____________________________________________________________________
Stop data transfer: A change in the state of the data
line from low to high while the clock line is high defines
the STOP condition.
Data valid: The state of the data line represents valid
data when, after a START condition, the data line is sta-
ble for the duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data. Figure 2 details how data transfer is accom-
plished on the 2-wire bus. Depending upon the state of
the R/W bit, two types of data transfer are possible.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
data bytes transferred between START and STOP con-
ditions is not limited and is determined by the master
device. The information is transferred byte-wise and
each receiver acknowledges with a ninth bit.
Within the bus specifications a regular mode (100kHz
clock rate) and a fast mode (400kHz clock rate) are
defined. The DS1805 works in both modes.
Acknowledge: Each receiving device, when addressed,
is obliged to generate an acknowledge after the recep-
tion of each byte. The master device must generate an
extra clock pulse that is associated with this acknowl-
edge bit.
A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable low during the high period of
the acknowledge-related clock pulse. Of course, setup
and hold times must be taken into account. A master
must signal an end of data to the slave by not generat-
ing an acknowledge bit on the last byte that has been
clocked out of the slave. In this case, the slave must
leave the data line high to enable the master to gener-
ate the STOP condition.
Data transfer from a master transmitter to a slave
receiver: The first byte transmitted by the master is the
control byte (slave address). Next follows a number of
data bytes. The slave returns an acknowledge bit after
each received byte.
Data transfer from a slave transmitter to a master
receiver: The first byte (the slave address) is transmit-
ted by the master. The slave then returns an acknowl-
edge bit. Next follows a number of data bytes
transmitted by the slave to the master. The master
returns an acknowledge bit after all received bytes
other than the last byte. At the end of the last received
byte, a ‘not acknowledge’ is returned.
The master device generates all of the serial clock
pulses and the START and STOP conditions. A transfer
is ended with a STOP condition or with a repeated
START condition. Since a repeated START condition is
also the beginning of the next serial transfer, the bus
will not be released.
The DS1805 can operate in the following two modes:
Slave receiver mode: Serial data and clock are
received through SDA and SCL. After each byte is
received, an acknowledge bit is transmitted. START and
STOP conditions are recognized as the beginning and
end of a serial transfer. Address recognition is performed
by hardware after reception of the slave address and
direction bit.
Slave transmitter mode: The first byte is received and
handled as in the slave receiver mode. However, in this
mode the direction bit will indicate that the transfer
direction is reversed. Serial data is transmitted on SDA
by the DS1805 while the serial clock is input on SCL.
START and STOP conditions are recognized as the
beginning and end of a serial transfer.
Slave Address
A control byte is the first byte received following the
START condition from the master device. The control
byte consists of a four-bit control code; for the DS1805,
this is set as 0101 binary for read/write operations. The
next three bits of the control byte are the device select
bits (A2, A1, A0). They are used by the master device
to select which of eight devices are to be accessed.
The select bits are the three least significant bits (LSB)
of the slave address. Additionally, A2, A1, and A0 can
be changed any time during a powered condition of the
part. The last bit of the control byte (R/W) defines the
operation to be performed. When set to a one, a read
operation is selected; when set to a zero a write opera-
tion is selected. Figure 3 shows the control byte struc-
ture for the DS1805.
Figure 3. Control Byte
MSB
DEVICE
IDENTIFIER
DEVICE
ADDRESS
READ/WRITE
BIT
0
1
0
1
A2
A1
A0
R/W
LSB
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